簡易檢索 / 詳目顯示

研究生: 黃泳森
Huang, Yong-Sen
論文名稱: 單相五階層換流器之實現
Implementation of a Single-Phase Five-Level Inverter
指導教授: 陳建富
Chen, Jiann-Fuh
共同指導教授: 楊宏澤
Yang, Hong-Tzer
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2020
畢業學年度: 108
語文別: 英文
論文頁數: 44
中文關鍵詞: 數位訊號處理器 (Digital Signal Processor,DSP)多階層換流器全橋換流器
外文關鍵詞: multilevel inverter, DSP (Digital Signal Processor), H-bridge inverter
相關次數: 點閱:93下載:0
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 本論文旨在研發五階層換流器,再引用實驗室畢業學長所研究的多階層架構,實現 DC-AC 能量轉換。主要架構包含6個功率開關實現五階層交流之輸出,架構為利用2個功率開關之輔助電路與傳統全橋電路所組成換流器以達到輸出,再藉由TMS320F28035 數位訊號處理器 (DSP) 控制功率開關來實現。本文中會說明此電路動作之原理、控制之流程及所提理論進行驗證。
    最後研製一200 V之直流電壓輸入、110 V之交流電壓輸出多階換流器,輸出功率為1.5 kW ,其滿載效率為93.1%,負載在759.5 W時有最大效率96.35%。此五階層換流器經由模擬與實驗之結果證明架構之可行性。

    In this thesis, a citing the multi-level architecture developed by the graduated seniors of the laboratory, a five-level inverter are implementation. The power stage includes 6 power switches to achieve the output voltage of AC. The structure uses an auxiliary circuit consisted of 2 power switches and a conventional H-bridge circuit to achieve the output, and then is controlled by the TMS320F28035 digital signal processor (DSP). The principle of this circuit operation and the flow of control with discussed in this thesis.
    Finally, a multilevel inverter with DC input voltage 200 V and output voltage 110 Vrms. The output power is 1.5 kW. Full load efficiency is 93.1%, the maximum efficiency in 759.5 W load is 96.35%. The feasibility of the five-level inverter are proved by the simulation and experiment results.

    CONTENTS Chinese Abstract……………………………………………………………I Abstract……………………………………………………………………II Acknowledgement…………………………………………………………III CONTENTS………………………………………………………………IV List of Tables………………………………………………………………VI List of Figures……………………………………………………………VII Chapter 1. Introduction……………………………………………………1 1.1 Backgrounds and Motivations………………………………………1 1.2 Research Purpose and Content………………………………………2 1.3 Organization of Thesis………………………………………………3 Chapter 2. Review of Multilevel Topologies………………………………4 2.1 Diode-Clamped Inverter…………………………………………4 2.2 Capacitor-Clamped Inverter………………………………………8 2.3 Cascaded H-Bridge Inverter……………………………………10 2.4 Simplified Multilevel Inverter……………………………………12 2.5 Sine Pulse Width Modulation……………………………………15 2.6 Conclusions of Existing Multilevel Topologies…………………17 Chapter 3. Analysis of Single-Phase Five-level Multilevel Inverter…18 3.1 Proposed Circuit Topology…………………………………………18 3.2 Mode Analysis of Proposed Topology……………………………19 3.3 Simplified Control Method of Proposed Topology………………25 Chapter 4. Simulation and Experimental Results………………………30 4.1 Specification of Circuit and Implementation of Control Method …30 4.2 Design of the Output Low-Pass Filter……………………………31 4.3 Simulation Results of the Proposed Topology…………………… 32 4.4 Experimental Results of the Proposed Topology……………… 35 Chapter 5. Conclusions and Future Works………………………………40 5.1 Conclusions………………………………………………………40 5.2 Future Works………………………………………………………41 References…………………………………………………………………42

    References
    [1] J. Rodríguez, J. S. Lai, and F. Z. Peng, “Multilevel Inverters: a survey of topologies, controls, and applications,” IEEE Trans. on Industrial. Electronics, Vol. 49, No. 4, pp. 724-738, August 2002.
    [2] S. Busquets-Monge, J. Rocabert, P. Rodríguez, S. Alepuz, and J. Bordonau, “Multilevel diode-clamped converter for photovoltaic generators with independent voltage control of each solar array,” IEEE Trans. on Industrial. Electronics, Vol. 55, No. 7, pp. 2713-2723, July 2008.
    [3] O. Bouhali, B. Francois, E. M. Berkouk, and C. Saudemont, “DC link capacitor voltage balancing in a three-phase diode clamped inverter controlled by a direct space vector of line-to-line voltages,” IEEE Trans. on Power Electronics, Vol. 22, No. 5, pp. 1636-1648, September 2007.
    [4] R. Abdullah, N. A. Rahim, S. R. Sheikh Raihan, and A. Z. Ahmad, "Five-Level Diode-Clamped Inverter With Three-Level Boost Converter," IEEE Tran. on Industrial. Electronics, Vol. 61, No. 10, pp. 5155-5163, October. 2014,
    [5] M. M. Renge and H. M. Suryawanshi, "Five-Level diode clamped inverter to eliminate common mode voltage and reduce dv/dt in medium voltage rating induction motor drives," IEEE Trans. on Power Electronics, vol. 23, no. 4, pp. 1598-1607, July 2008.
    [6] S. Karugaba, A. Muetze, and O. Ojo, “On the common-mode voltage in multilevel multiphase single- and double-ended diode-clamped voltage-source inverter systems,” IEEE Trans. on Industry. Applications, Vol. 48, No. 6, pp. 2079-2091, November/December 2012.
    [7] X. Yuan and I. Barbi, ” Fundamentals of a new diode clamping multilevel inverter,” IEEE Trans. on Power Electronics, Vol. 15, No. 4, pp.711-718, July 2000.
    [8] D. W. Kang, B. K. Lee, J. H. Jeon, T. J. Kim, and D. S. Hyun, “A symmetric carrier technique of CRPWM for voltage balance method of flying-capacitor multilevel inverter,” IEEE Trans. on Industrial. Electronics, Vol. 52, No. 3, pp. 879-888, June 2005.
    [9] A. Shukla, A. Ghosh, and A. Joshi, “Hysteresis current control operation of flying capacitor multilevel inverter and its application in shunt compensation of distribution systems,” IEEE Trans. on Power Delivery, Vol. 22, No. 1, pp. 396-405, January 2007.
    [10] M. Khazraei, H. Sepahvand, K. A. Corzine, and M. Ferdowsi, “Active capacitor voltage balancing in single-Phase flying-Capacitor multilevel power converters,” IEEE Trans. on Industrial. Electronics, Vol. 59, No. 2, pp. 769-779, February 2012.
    [11] I. D. Kim, E. C. Nho, H. G. Kim, and J. S. Ko, “A generalized undeland snubber for flying capacitor multilevel inverter and converter,” IEEE Trans. on Industrial. Electronics, Vol. 51, No. 6, pp. 1290-1296, December 2004.
    [12] A. Shukla, A. Ghosh, and A. Joshi, “Improved multilevel hysteresis current regulation and capacitor voltage balancing schemes for flying capacitor multilevel inverter,” IEEE Trans. on Power Electronics, Vol. 23, No. 2, pp. 518-529, March 2008.
    [13] M. Sharifzadeh, H. Vahedi, R. Portillo, L. G. Franquelo, and K. Al-Haddad, “Selective Harmonic Mitigation Based Self-Elimination of Triplen Harmonics for Single-Phase Five-Level Inverters,” IEEE Trans.on Power Electronics, Vol. 34, No. 1, pp. 86-96, January. 2019
    [14] P. Lezana, J. Rodriguez, and D. A. Oyarzun, “Cascaded multilevel inverter with regeneration capability and reduced number of switches,” IEEE Trans.on Industrial. Electronics., Vol. 55, No. 3, pp. 1059–1066, March 2008.
    [15] L. Zhang, K. Sun, M. Gu, D. Xu, and Y. Gu, "A capacitor voltage balancing control method for five-level full-bridge grid-tied inverters without split-capacitor voltage sampling," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 6, no. 4, pp. 2042-2052, Dec. 2018.
    [16] A. K. Gupta and A. M. Khambadkone, "A general space vector PWM algorithm for multilevel inverters, including operation in overmodulation range," IEEE Trans. on Power Electronics, vol. 22, no. 2, pp. 517-526, March 2007.
    [17] F. Gao, "An enhanced single-phase step-up five-level inverter," IEEE Trans. on Power Electronics, vol. 31, no. 12, pp. 8024-8030, Dec. 2016
    [18] A. Chen and X. He, “Research on hybrid-clamped multilevel-inverter topologies,” IEEE Trans. Industrial. Electronics, Vol. 53, No. 6, pp. 1898 - 1907, Dec. 2010.
    [19] C. Rech and J. R. Pinheiro, “Hybrid multilevel converters: unified analysis and design considerations,” IEEE Trans. on Industrial. Electronics., Vol. 54, No. 2, pp. 1092–1104, April 2007.
    [20] R. Gupta, A. Ghosh, and A. Joshi, “Switching characterization of cascaded multilevel-inverter-controlled systems,” IEEE Trans. on Industrial. Electronics., Vol. 55, No. 3, pp. 1047–1058, March 2008.
    [21] A. Ghazanfari, H. Mokhtari and M. Firouzi, “Simple Voltage Balancing Approach for CHB Multilevel Inverter Considering Low Harmonic Content Based on a Hybrid Optimal Modulation Strategy,” IEEE Trans. on Power Delivery, Vol. 27, No. 4, pp. 2150-2158, October. 2012
    [22] G. Ceglia, V. Guzmán, C. Sánchez, F. Ibáñez, J. Walter, and M. I. Giménez, “A new simplified multilevel inverter topology for DC–AC conversion,” IEEE Trans. on Power Electronics, Vol. 21, No. 5, pp. 311-1319, September 2006.
    [23] M. Ahmed and S. Mekhilef, “ Three-Phase Three-Level voltage source inverter with a Three-Phase Two-Level inverter as a main circuit,” 4th IET Conference on Power Electronics, Machines and Drives 2008, April 2-4, pp. 640-644.
    [24] N. A. Rahim, K. Chaniago, and J. Selvaraj, “Single-Phase seven-level grid-connected inverter for photovoltaic system,” IEEE Trans. on Industrial. Electronics, Vol. 58, No. 6, pp. 2435-2443, June 2011.
    [25] C. L. Chen, Y. Wang, J. S. Lai, Y.S. Lee, and D. Martin, “Design of parallel inverters for smooth mode transfer microgrid applications,” IEEE Trans. on Power Electronics, Vol. 25, No. 1, pp. 6-15, Jan. 2010.
    [26] J. S. Lai and F. Z. Peng, “Multilevel Converters–A new breed of power converters,” IEEE Trans. on Industry. Applications, Vol. 32, pp. 509–517, May/June 1996
    [27] E. Najafi and A. H. M. Yatim, “Design and implementation of a new multilevel inverter topology,” IEEE Trans. on Industrial. Electronics, vol: 59, No. 11, pp. 4148-1454, Nov. 2012.
    [28] N. A. Rahim and J. Selvaraj, "Multistring five-level inverter with novel PWM control scheme for PV application," IEEE Trans. on Industrial Electronics, vol. 57, no. 6, pp. 2111-2123, June 2010.
    [29] G. E. Valderrama, G. V. Guzman, E. I. Pool-Mazún, P. R. Martinez-Rodriguez, M. J. Lopez-Sanchez, and J. M. S. Zuñiga, "A single-phase asymmetrical T-Type five-level transformerless PV inverter," IEEE Journal of Emerging and Selected Topics in Power Electronics, vol. 6, no. 1, pp. 140-150, March 2018
    [30] 蔡佳原,“單相新型多階層換流器研製”,國立成功大學電機工程研究所碩士論文,2012。
    [31] 高聖凱,“多階層換流器電容性與電感性負載探討”,國立成功大學電機工程研究所碩士論文,2014。

    下載圖示 校內:2025-08-20公開
    校外:2025-08-20公開
    QR CODE