本論文實作具死區時間自我探勘之無感測數位式穩壓器，使用逐漸嶄露頭角的數位電源技術，無需任何功率級或電流感測元件，實現控制器搜尋最佳化死區，能有效提升電源轉換器效率，延長電池使用壽命。同時，也提出加速搜尋最佳化死區的機制，能大幅縮短搜尋時間，快速達到目標。此外，為了避免因為死區解析度太低，而尋找到非最佳化死區時間，使用延遲電路串的方式實現，可不必需要高頻率的操作即可提高死區解析度。本論文以FPGA為實驗平台，進行量測並驗證所提出之概念，證明確實能大幅縮短搜尋時間及提昇效率。最後將已在FPGA驗證過的電路架構整合delay-line ADC以TSMC 1P6M 0.18um製程下線並量測驗證，晶片大小為1.3 mm2且量測結果也與預期相符。

This thesis presents a sensorless digital regulator with dead-time self-exploration. The dead-time controller utilizes the relationship between duty-cycle command and power-loss to find the optimized dead-time without sensing any of the power-stage signals. A exploration algorithm with delay-line circuits instead of high frequency is used to accelerate the optimized dead-time searching and provides high quantization resolution with dead-time step. This approach is well suited for digital IC implementation. The FPGA experimental results show that the proposed architecture can quickly search the optimization of the dead-time and improve efficiency. After FPGA prototyping, the proposed DC-DC converter has been implemented in TSMC 1P6M 0.18μm CMOS technology. The chip size is 1.3 mm2 and the experimental results proved the same with FPGA experimental results.

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