成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	林維新 Lin, Wei-Xin
論文名稱：	探索以可繞度為導向且能考慮設計階層之三維積體電路設計流程 Exploration of Routability-Driven 3-D IC Design Flow Considering Design Hierarchy
指導教授：	林家民 Lin, Jai-Ming
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2020
畢業學年度：	109
語文別：	英文
論文頁數：	27
中文關鍵詞：	三維電路擺置、可繞度、設計階層
外文關鍵詞：	3-D IC placement, routability, design hierarchy
相關次數：	點閱：113 下載：0
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

為了在IC Compiler上實作一個三維電路設計，這篇論文提出一個藉由IC Compiler將二維電路設計轉換成三維電路設計的方法。因為IC Compiler沒辦法進行大模塊和矽穿孔擺置的合法化，所以這篇論文將一個新穎的模塊擺置演算法和一個基於貪婪演算法的矽穿孔擺置合法化方法整合到三維電路設計流程中。此外，為了降低三維多階層全域擺置的時間，這篇論文提出一個連線分解方式，將電路依據當前擺置結果進行分解，並且同時執行每個子電路的擺置和優化。為了將繞線壅擠的優化方法也考慮到三維擺置當中，這篇論文比較了兩個以可繞度為導向的擺置演算法的優劣，此兩個演算法由實驗結果得出，是當前較佳的兩個繞線擁擠優化方法。最後這篇論文提出一個新的基於動態擴張元件面積的數學解析法來解決可繞度問題。

In order to implement a 3-D design in the IC Compiler, this paper proposes a method to transform a 2-D design into a 3-D design by the IC Compiler. Because the IC Compiler cannot legalize the positions of macros and TSVs, a novel macro placement algorithm and a greedy TSV legalization strategy are applied in this paper. In addition, to reduce the runtime of a 3-D multilevel global placement, this paper proposes a netlist decomposition method to partition a netlist according to the placement result and solve the non-linear placement problem of each sub-netlist independently and simultaneously. To invoke a routing overflow refinement in a 3-D placement, this paper compares the pros and cons of two state-of-the-art routability-driven placement and proposes a new analytical formulation with dynamic cell inflation.

摘要	I
Abstract	II
誌謝	III
Table of Contents	IV
List of Figures	V
Chapter 1	Introduction	1
1.1	3-D IC Design	3
1.2	Our Contributions	4
Chapter 2	Preliminaries	5
2.1	Analytical Placement and Hierarchy Cluster	5
2.2	Macro Placement	6
Chapter 3	3-D IC Design Flow	7
3.1	Partitioning	7
3.2	TSV Insertion and 3-D Global Placement	8
3.3	Routing	11
Chapter 4	3-D Global Placement	12
4.1	Macro Placement	12
4.2	Fast 3-D Multilevel Global Placement	14
4.3	Routability Optimization	16
4.4	Legalization	19
Chapter 5	Experimental Results	21
Chapter 6	Conclusion	24
Bibliography	25
 List of Figures
Figure 1 1: 3-D IC layout in the IC Compiler.	2
Figure 1 2 The model of two TSVs in silicon substrate.	2
Figure 1 3: Simulation result of normal stress.	3
Figure 1 4: 3-D IC layout in the IC Compiler.	4
Figure 2 1: Design hierarchy-guided clustering.	6
Figure 3 1: 3-D IC design flow.	8
Figure 3 2: An example of Hierarchy-aware partition. (a) Original design. (b) New design with all hierarchical and physical blocks. (c) Module partition and merge.	9
Figure 3 3: An example of a 3-D net.	10
Figure 3 4: TSV insertion procedure.	10
Figure 4 1: Example of  (a) initial quadratic placement and (b) multilevel mixed-size placement result.	13
Figure 4 2: Fast 3-D multilevel global placement.	15
Figure 4 3: An example of the parallelization scheme of our fast 3-D multilevel global placement.	15
Figure 4 4:  (a) Wirelength-driven placement result. (b) The placement result with pin density constraint.	18
Figure 4 5: Legalization flow.	19
Figure 4 6: Legalization result in the IC Compiler.	20
                                    

[1] Synopsys Inc. https://www.synopsys.com/company.html.
[2] Himax Inc. http:www.himax.com.tw/zh/company/about-himax/
[3] Y. Cheon, and M.D.F. Wong, “Design hierarchy-guided multilevel circuit partitioning,” IEEE Trans. of TCAD, vol. 22, pp. 420--427, April 2003.
[4] T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace3: An analytical placer for large-scale mixed-size designs with pre-placed blocks and density constraints,” IEEE Trans. of TCAD, vol. 27, no. 7, pp. 1228--1240, 2008.
[5] J. Cong, and Y. Zou, “Parallel multi-level analytical global placement on graphics processing units,” in Proc. of ICCAD, Nov. 2009.
[6] Y.-L. Chuang, G.-J. Nam, C. J. Alpert, Y.-W. Chang, J. Roy, and N. Viswanathan, “Design-hierarchy aware mixed-size placement for routability optimization,” in Proc. of ICCAD, pp. 663--668, 2010.
[7] M.-K. Hsu, V.M. Balabanov, and Y.-W. Chang, “TSV-Aware Analytical Placement for 3-D IC Designs Based on a Novel Weighted-Average Wirelength Model,” IEEE Trans. of TCAD, vol. 32, pp. 497--509, March 2013.
[8] M.-K. Hsu, Y.-F. Chen, C.-C. Huang, S. Chou, T.-H. Lin, T.-C. Chen, and Y.-W. Chang, “NTUplace4h: A novel routability-driven placement algorithm for hierarchical mixed-size circuit designs,” IEEE Trans. of TCAD, vol. 33, no. 12, pp. 1914--1927, 2014.
[9] C.-C. Huang, H.-Y. Lee, B.-Q. Lin, S.-W. Yang, C.-H. Chang, S.-T. Chen, and Y.-W. Chang, “NTUplace4dr: A detailed-routing-driven placer for mixed-size circuit designs with technology and region constraints,” IEEE Trans. of TCAD, vol. 37, no. 3, pp. 669--681, 2018.
[10] Z.-W. Jiang, B.-Y. Su, and Y.-W. Chang, “Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs,” in Proc. of DAC, 2008.
[11] H.-R. Jiang, “Generic integer linear programming formulation for 3D IC partitioning,” in Proc. of SOCC, Jan. 2010.
[12] M. Jung, J. Mitra, D.Z. Pan, and S.-K. Lim, “TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC,” IEEE Trans. of TCAD, vol. 31, pp. 1194--1207, Aug. 2012.
[13] G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, “Multilevel Hypergraph Partitioning: Application in VLSI Domain,” IEEE Trans. of VLSI, vol. 7, pp. 69--79, March 1999.
[14] D.-H. Kim, K. Athikulwongse, and S.-K. Lim, “Study of Through-Silicon-Via Impact on the 3-D Stacked IC Layout,” IEEE Trans. of TVLSI, vol. 21, pp. 862--874, May 2013.
[15] G. Luo, Y. Shi, and J. Cong, “An Analytical Placement Framework for 3-D ICs and Its Extension on Thermal Awareness,” IEEE Tran. of TCAD, vol. 32, pp. 510--523, April 2013.
[16] S. Li, and C.-K. Koh, “Analytical placement of mixed-size circuits for better detailed-routability,” in Proc. of ASP-DAC, Jan. 2014.
[17] J.-M. Lin, S.-T. Li, and Y.-T. Wang, “Routability-driven mixed-size placement prototyping approach considering design hierarchy and indirect connectivity between mac-ros,” in Proc. of DAC, 2019.
[18] J.-M. Lin, Y.-L. Deng, S.-T. Li, B.-H. Yu, L.-Y. Chang, and T.-W. Peng, “Regularity-aware routability-driven macro placement methodology for mixed-size circuits with obstacles,” IEEE Tran. of TVLSI, vol. 27, no. 1, pp. 57--68, 2019.
[19] H. Park, B.-W. Ku, K. Chang, D.-E. Shim, and S.-K. Lim, “Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs,” in Proc. of ISPD, March 2019.

校內：2025-11-30公開
校外：2025-11-30公開

簡易檢索 / 詳目顯示

相關論文