隨著半導體的特徵尺寸持續地縮小以及目前晶片的設計複雜度明顯地上升，在現今晶片的電源網路規劃時面臨到越來越多的挑戰，並且需要在元件擺置階段結束後進行電源網路最佳化。大多數現有的電源網路最佳化方法都致力於如何通過調整電源線段的尺寸來滿足電壓降限制。為了建構一個以可繞度為導向的電源網路，本篇論文開發一種以多種手段去高效且高效率最佳化電源網路的方法，包含電源線段形變階段、電源線段插入階段以及調整電源線段尺寸階段。首先，為了增加電源網路擺置的靈活性，在形變階段會將電源線段分成幾小段並調整它們的位置以減少局部區域的繞線擁擠度。接下來，我們在插入階段中應用兩種不同方法去插入額外的電源線段以最小化電壓降效應。第一個是局部性插入方法，在方法中會根據每個區域對電壓降的影響將電源線段插入到該區域中。另一個則是全域性插入方法，在方法中會藉由違反電壓降限制的點去建構最小直線距離史坦納樹，並且利用單調繞線演算法去決定插入的電源線段的位置。和初始的電源網路相較之下，我們提出的方法不僅可以有效低消除電壓降違規同時對繞線擁擠度的影響也比較小。實驗結果顯示，我們的方法可以工業設計中獲得十分不錯的結果。

As the feature size of semiconductor shrinks and the complexity of modern design increases significantly, power delivery network (PDN for short) optimization faces more and more challenges. In addition, classic PDN optimizing methods only focus on how to meet the constraints by resizing size of power stripes. This paper develops an efficient and effective PDN optimizing method including many ways to construct a routability-driven PDN. Our method includes a deforming step, two inserting steps and a sizing step to modify the topology of a PDN. We adopt the row-style based PDN for the deforming step to facilitate routabiliy of signal nets. For inserting step, one is a local insertion method which inserts power stripes according to factors that influence IR-drop. The other is a global insertion method which builds rectilinear Steiner minimal trees (RSMTs for short) and applies monotonic routing algorithm to determine the positions of additional power stripes. Compared to the original PDN, the proposed method can not only eliminate voltage violations efficiently but also consume a little power routing resource and induce a little routing congestion. The experimental results show that our method achieves promising results in industry designs.

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