電腦運算架構中處理器的運行速度日益遞增，與記憶體間的效能隔閡也
隨之擴大，被視為整體效能的關鍵瓶頸之一。應用無損資料壓縮演算法於記憶體階層，當記憶體資料以壓縮型態傳輸，可間接地增加記憶體可用容量或減少頻寬傳遞，提升系統整體效能。本論文提出一個針對浮點數表示法開發的低延遲記憶體壓縮架構，但同時支援浮點數與整數格式資料。以快取區塊為壓縮單位並選定參考基底，分析記憶體資料的可壓縮特性後，設計低硬體延遲的壓縮演算法程序，避免抵銷壓縮技術的好處。透過實驗證明，所提出的壓縮架構在眾多測試基準下，可提供平均50.18% 的資料壓縮率。於圖形處理器(Graphic Processing Unit, GPU) 整合階段，套用記憶體I/O 連接壓縮架構可減少約45% 的記憶體頻寬使用，並藉由DRAMPower 與Primetime 來評估對於存取記憶體功耗的改善。

As the speed of contemporary computer architecture increases, there is a continuous growing gap between processor and memory. Even though we can increase the
capacity or bandwidth, the memory is still a critical part for the data-intensive applications. Data compression is a promising approach to resolve this issue by reducing the data size. In general-purpose graphics processing unit (GPGPU), many parallel computing applications have large amounts of single precision floating-point data.
However, most prior compression algorithms of memory have been designed for integer data composition. In this paper, we propose an innovative compression algorithm of low latency decompression for GPGPU. Both floating-point and integer in-memory data can be effectively compressed while introducing minimal affection on access latency and hardware complexity. Simulation results demonstrate that our compression algorithm can significantly reduce data size by an average compression ratio of 50.18%. By integrating the proposed architecture with the memory I/O
controller, the GPU will reduce 45% of the memory bandwidth usage for huge data transfer.

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