由於電源網路對電路的效能有很大的影響，因此電源網路規劃(Powerplanning)仍然被視為現今的實體設計(Physical Design)流程當中最為重要的階段。隨著半導體製程的進步和設計複雜性的增加，導致電源網路規劃問題難度大幅度提高。為了滿足電壓下降和電遷移效應的約束，傳統的電源網路規劃法通常會使用過多的電源網路線，使得其在繞線階段時晶片上產生不可繞的區域。此外，他們忽略動態功率對電源網路的影響。因此現在電源網路規劃的挑戰為如何在滿足靜態壓降約束時同時最小化繞線資源使用量。更重要的是，必須在滿足動態壓降約束的同時考慮晶片的可繞度。
不同於以往的研究，在本論文中，我們開發了一個可靠且有效的電源網路規劃法，在考慮不同功率資料下達成以可繞度為導向之電源網路，可以在滿足壓降約束的同時還能夠最小化繞線面積。我們的方法包含規劃階段和優化階段。在規劃階段，我們在同時考量電壓下降和整體繞線擁擠度的情況下，使用叢集演算法來決定每條電源網路線的適當位置。為了滿足動態壓降約束，優化階段會藉由多個功率資料下的壓降違規圖建立出代表性的違規圖，並依據該圖改善壓降違規。根據我們所提出的方法可以有效地解決壓降違規，並且不會使用過多的繞線資源。實驗結果顯示，此方法能在實際工業使用之電路取得了不錯的成果。

Because a power network has a great impact on the performance of a circuit, powerplanning has become a more important stage in a modern VLSI design flow. As the semiconductor feature size shrinks and the design complexity increases, powerplanning becomes more difficult. In order to meet the IR-drop and EM constraints, traditional powerplanning often uses excessive power stripes which may lead to routing congestion in signal net routing. Moreover, they only consider the static power consumption without considering the dynamic power consumption. Hence, the challenges of modern powerplanning problem include how to minimize routing resources while satisfying the static IR-drop constraint. More importantly, it has to consider routability while meeting the dynamic IR-drop constraint.
In this thesis, we develop an efficient and effective powerplanning methodology to construct a routability-driven power network for different power profiles, which can minimize routing area while satisfying the IR-drop constraint. Our methodology consists of the planning stage and post-optimization stage. In the planning stage, we apply the clustering based algorithm to determine the proper locations of power stripes, where the IR-drop and routing congestion are considered at the same time. In order to consider dynamic IR-drop constraint, the post-optimization stage iteratively constructs a representative voltage violation map according to multiple power profiles and repair IR-drop violations according to the map. According to the proposed approach, our approach can repair voltage violations efficiently without consuming excessive routing area. The experimental results show the proposed methodology achieves promising results in industry designs.

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