本論文提出一個具有尾電流控制電路及電源漣波隔離機制之低壓降線性穩壓器。尾電流控制電路由兩組差動對輸入、5-bit數位類比轉換器、及電流總和電路所組成，可藉由調整外部的控制訊號改變尾電流的比例，使低壓降線性穩壓器的輸出具有5-bit可調輸出電壓範圍。加入電源漣波隔離機制可以有效的改善寬頻域的電源拒斥效能。
本電路使用TSMC 0.18um 1-Poly 6-Metal CMOS標準製程技術。在輸入電壓為1.6V、負載電流為5mA的情況下，量測結果為: 輸出電壓具有5-bit的可調輸出電壓範圍由1V至1.2V。加入電源漣波隔離機制可以有效的改善約20dB的電源拒斥效能至1MHz的頻率範圍達。由量測結果顯示，本論文所提出之低壓降線性穩壓器可透過外部控制訊號調整輸出電壓並且達到寬頻域的高電源拒斥效能，適合於系統晶片(SoC)應用。

A low-dropout (LDO) regulator with a tail current control (TCC) circuit and a supply ripple isolation mechanism is presented in this thesis. The TCC circuit consists of a dual differential pair, a 5-bit current DAC, and a current summation circuit, which can adjust the tail current ratio to achieve 5-bit programmable output using external control signals. The supply ripple isolation mechanism is added to improve the power supply rejection (PSR) over a wide frequency range.
The proposed design is fabricated in the TSMC 0.18μm 1-poly 6-metal CMOS process. Experimental results show that the supply is 1.6V and that the output is a 5-bit programmable output voltage ranging from 1V to 1.2V with a maximum load current of 5mA. The LDO regulator achieves a worst-case PSR performance of -20dB over 1MHz. The results show that the proposed design is suitable for system-on-chip (SoC) applications, where the output voltage can be changed using external control signals and achieve high PSR over a wide frequency range.

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