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研究生： 張簡中泰
Chang-Cheng, Chung-Tai
論文名稱： 基於時間局限性和空間局限性之工作負載感知快閃記憶體轉譯層
A Workload-Aware Flash Translation Layer Exploiting both Temporal and Spatial Localities
指導教授： 張大緯
Chang, Ta-Wei
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 資訊工程學系
Department of Computer Science and Information Engineering
論文出版年： 2011
畢業學年度： 100
語文別： 英文
論文頁數： 39
中文關鍵詞： 快閃記憶體 、轉譯層 、時間局限性 、空間局限性
外文關鍵詞： NAND flash, Erase before Write, FTL, Temporal Locality, Spatial Locality
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    • 快閃記憶體已經被預期當作下一世代的儲存裝置。而且世面上已有諸多的產品使用快閃記憶體成為他們的儲存裝置。例如:數位相機、手機、、、等3C產品。但是快閃記憶體在執行寫入動作之前必須先執行抹除，並且寫入與抹除的單位大小不一樣，寫入的單位是page，而抹除的單位是block(64或32pages)，而此問題藉由轉譯層來輔助硬體的運作。然而轉譯層在執行抹除動作之前必須先把block裡面有效的資料page搬移至其他block，因此如果需要搬移的資料(pages)越多，就會使得系統的效能降低，假若我們讓block在要被抹除的時候，裡面所剩下的都是無效的資料，那我們將無須執行搬移動作，而在同一個block的page可以同時成為無效的page，表示他們具有相同或相近的特性。因此在執行寫入動作時，若能把特性相同的page集中在同一個block，將可大大減少在抹除動作所需搬移的page。
    所以我們藉由使用並調整時間局限性和空間局限性來使整個系統達到最佳的效能。

    NAND flash packages have been expected as the next generation storage device. But there are more and more products using NAND flash packages into their storage device. Such as digital cameras, mobile phones,,, etc. But Flash must perform erase operation before performing write operation. However, the unit sizes of write and erase are different, the former is one page and the later is one block which is composed of 64 or 32Pages, so it will come out a problem that if there are some pages still alive in the block we want to erase, we have to move those pages to other block before we erase the physical block. The manufacture deal with this problem by a software called Flash Translation Layer. Valid page coping decrease the performance, but if we can move fewer pages, then we can get better performance and it can be done by gathering the pages which has the same locality, for the pages having the same locality will be live or dead together.
    We exploit temporal and spatial localities to improve the performance by gathering the pages with the same locality into the same physical block, so we can decrease the live pages in the ready to be erased block.

    Chapter 1 Introduction...................................1 Chapter 2 Background and Related Work....................3 2.1 NAND Flash Memory....................................3 2.2 Flash Translation Layer (FTL) .......................4 2.3 Data Clustering (DAC) ...............................5 Chapter 3 Motivation.....................................7 3.1. Page Identification with Two Localities.............7 3.1.1 Temporal Locality .................................7 3.1.2 Drawbacks in DAC...................................7 3.1.3 Spatial Locality ..................................8 3.2 Detecting Appropriate Partition Size for each Workloads................................................8 Chapter 4 Design and Implementation of Workload Aware Partition Size (WPAS)…..................................10 4.1 Logical Space Arrangement...........................11 4.2 Merge...............................................11 4.3 Split...............................................12 4.4 How to decide to merge or split.....................13 4.4.1 Computing a score for each configuration..........13 4.5 Detecting Closing Update Time ......................19 4.6 Algorithm and Threshold.............................20 Chapter 5 Performance Evaluation........................22 5.1 Experimental Environment............................22 5.2 Performance Evaluation..............................25 5.2.1 Improvement from DAC, STA and STA_DAC.............25 5.2.2 Performance of Fixed Size STA_DAC and WAPS........27 5.2.3 Workload Awareness................................27 5.3 Threshold Value.....................................29 5.3.1 Threshold of Merge ...............................29 5.3.2 Threshold of Split ...............................30 5.3.3 Adjustment Period.................................31 5.3.4 Threshold of Agreement............................32 5.4 Adjustment Phase....................................33 5.5 Partition Size at Adjustment Phase..................34 Chapter 6 Conclusion....................................36 Chapter 7 Future Work...................................36 Reference...............................................37

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