簡易檢索 / 詳目顯示

研究生: 翟德翔
Jair, De-Xiang
論文名稱: 編碼型快閃記憶體用於記憶體內運算類神經網路應用
Compute in Memory of NOR Flash in Neural Networks
指導教授: 江孟學
Chiang, Meng-Hsueh
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年: 2023
畢業學年度: 111
語文別: 英文
論文頁數: 76
中文關鍵詞: 編碼型快閃記憶體 、深度學習 、類神經網路 、HSPICE 、TensorFlow 、Python 、Verilog-A
外文關鍵詞: Flash memory, Deep Learning, Neural Network, HSPICE, TensorFlow, Python, Verilog-A
相關次數: 點閱:187  下載:2 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報
  • 近年來,人工智慧的發展呈現爆炸式成長,一般熟知的人工智慧運算單元功耗大的問題也一一浮現,於是類神經網路的元件及電路要求也勢必提高,低耗能、快速讀取速度、高可靠度的優點使編碼型快閃記憶體(NOR Flash)為非常有潛力的元件。本篇論文旨在探討利用實際量測的常溫編碼型快閃記憶體的數據,利用硬體描述語言Verilog-A建立編碼型快閃記憶體(NOR Flash)模型,同時萃取元件物理特性,以電路模擬軟體(HSPICE)測試電性,同時萃取元件物理特性,藉由輸入偏壓(或電流)改變元件電導。取出元件對於類神經網路所需的參數。
    另外,模型提供多階式儲存單元功能,預期能提高記憶體元件電路設計效率;權重計算模組能提供不同電導值,模擬仿生網路之類比行為操作的能力,並利用深度學習軟體(TensorFlow)建立類神經網路,進行權重與演算法的訓練,能夠預測長期增強(LTP)、長期漸弱(LTD)等類比行為的功耗及達成手寫圖形資料辨識能力,並對編碼型快閃記憶體做出不同改變,使類神經網路有更高的手寫圖形資料辨識準確率及功耗更有效率。

    In recent years, the development of artificial intelligence (AI) has witnessed explosive growth. However, the well-known issue of high-power consumption in AI computing units has also emerged. Consequently, there is a growing demand for neural network components and circuits that offer low power consumption, fast read speeds, and high reliability. In this context, NOR Flash memory, with its advantages of low power consumption, fast read speeds, and high reliability, has emerged as a promising component.
    The objective of this paper is to explore the utilization of experimentally measured data from commercially available NOR Flash memory devices at room temperature. Using the hardware description language Verilog-A, a model for NOR Flash memory is developed, and the physical characteristics of the device are extracted. The model is then tested using circuit simulation software (HSPICE) to evaluate its electrical behavior. By varying the input bias voltage or current, the conductance of the memory cells can be adjusted. The model extracts the parameters required for neural network applications.
    Furthermore, the model provides a multi-level storage unit functionality, which is expected to enhance the efficiency of memory component circuit design. The weight calculation module offers different conductance values, allowing for the simulation of analog-like operations in bio-inspired networks. The deep learning software TensorFlow is used to build a neural network for training the weights and algorithms. The network can predict long-term potentiation (LTP), long-term depression (LTD), and other analog-like behaviors, while considering the power consumption. It achieves handwriting recognition capabilities and improves the accuracy and power efficiency of handwriting data recognition by making various modifications to the NOR Flash memory.

    摘要 i Abstract ii 誌謝 iv Contents vii Table Captions ix Figure Captions x Chapter 1 Introduction 1 1.1 Background 1 1.2 Research Motivation 4 1.3 Introduction to Software 4 1.4 Chapter Architecture 5 Chapter 2 Literature Review 6 2.1 Introduction to Flash Memory 6 2.1.1 Fundamental of Flash Memory 6 2.1.2 Mechanism of the Transformation of Resistance 8 2.1.3 Reliability of Flash Memory 13 2.2 The Architecture of Flash Memory Array 14 2.2.1 NAND Flash 14 2.2.2 NOR Flash 15 2.2.3 Comparison Between NAND and NOR 16 2.3 Synapse Array Architecture 18 2.3.1 Artificial Neural Network 18 2.3.2 Hardware NVM-Based Array Structure 25 Chapter 3 Experiment Methodology 30 3.1 NOR Flash Data and Manipulation 30 3.2 Modified CIMulator Model 36 3.2.1 Weight Design 36 3.2.2 Training Process in Hardware 41 3.2.3 Power Consumption 44 3.3 Process of Inference 46 Chapter 4 Result and Discussion 49 4.1 Initial Data Simulation 51 4.2 Incremental Step Pulse Programming (ISPP) with Special Pulse Supply 61 4.3 High Resolution of Pulse Numbers 66 Chapter 5 Conclusion and Future Work 70 References 71 Appendix 75

    [1] Aurélien Yol: “The difference between AI, Deep Learning, Machine Learning in agriculture”, 11 June 2021. Link: https://www.dilepix.com/en/blog/difference-artificial-intelligence-deep-learning-agriculture
    [2] J. Backus, “Can programming be liberated from the von neumann style?: A functional style and its algebra of programs,” Commun. ACM, vol. 21, no. 8, pp. 613–641, Aug. 1978. [Online]. Available: http://doi.acm.org/10.1145/359576.359579
    [3] Xiaohe Huang, Chunsen Liu, Yu-Gang Jiang, and Peng Zhou: “In-memory computing to break the memory wall” State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433, China and School of Computer Science, Fudan University, Shanghai 200433, China
    [4] Syuan-Hao Sie; Jye-Luen Lee; Yi-Ren Chen; Zuo-Wei Yeh; Zhaofang Li; Chih-Cheng Lu; Chih-Cheng Hsieh; Meng-Fan Chang; Kea-Tiong Tang: “MARS: Multimacro Architecture SRAM CIM-Based Accelerator With Co-Designed Compressed Neural Networks”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 41, Issue: 5, May 2022)
    [5] Shimeng Yu , Senior Member, IEEE, Wonbo Shim , Xiaochen Peng , Graduate Student Member, IEEE, and Yandong Luo: “RRAM for Compute-in-Memory: From Inference to Training”, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 68, NO. 7, JULY 2021
    [6] Dayane Reis, Michael Niemier, and X. Sharon Hu: “Computing in memory with FeFETs”, 23 July 2018
    [7] SemiWiki: The open forum for semiconductor professionals. Link: https://semiwiki.com/semiconductor-manufacturers/tsmc/287672-in-memory-computing-for-low-power-neural-network-inference/
    [8] Geoffrey W. Burr, Senior Member, IEEE, Robert M. Shelby, Severin Sidler, Carmelo di Nolfo, Junwoo Jang, Irem Boybat, Student Member, IEEE, Rohit S. Shenoy, Member, IEEE, Pritish Narayanan, Member, IEEE, Kumar Virwani, Member, IEEE, Emanuele U. Giacometti, Bülent N. Kurdi, and Hyunsang Hwang, Member, IEEE “Experimental Demonstration and Tolerancing of a Large-Scale Neural Network (165 000 Synapses) Using Phase-Change Memory as the Synaptic Weight Element”
    [9] Mythic: Compute-in-Memory. Link: https://mythic.ai/technology/compute-in-memory/
    [10] Yuxin Zhang, Sitao Zeng, Zhiguo Zhu, Zhaolong Qin, Chen Wang, Jingjing Li, Sanfeng Zhang, Yajuan He, Chunmeng Dou, Xin Si1, Meng-Fan Chang, Qiang Li: “A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash based Computation-in-Memory Structure for Machine Learning”
    [11] X. Guo , F. Merrikh Bayat , M. Prezioso , Y. Chen , B. Nguyen , N. Do , and D. B. Strukov: “Temperature-Insensitive Analog Vector-by-Matrix Multiplier Based on 55 nm NOR Flash Memory Cells ”
    [12] F. Douglis et al., “Storage Alternatives for Mobile Computers,” In Proc. OSDI, 1994.
    [13] Tutorials – TensorFlow, available online: https://www.tensorflow.org/tutorials.
    [14] 洪瑋辰(2019),“類比非揮發記憶體仿生電路之深度學習模擬平台”,國立成功大學微電子所碩士論文
    [15] F. Masuoka, M. Asano, H. Iwahashi, T. Komuro, and S. Tanaka, A new Flash E2PROM cell using triple polysilicon technology, Technical Digest-International Electron Devices Meeting, 464 (1984).
    [16] Fujio Masuoka, US Patent 4531203
    [17] 柯伯賢(2014)。氮化二氧化鈦作為電荷捕捉層在非揮發性記憶體中之研討。
    [18] 陳宥任(2007)。金奈米粒子和硒化鎘量子點於非揮發性記憶體元件電荷捕獲中心之研究。
    [19] B. Eitan and D. Frohman-Bentchkowsky, "Hot-electron injection into the oxide in n-channel MOS devices," in IEEE Transactions on Electron Devices, vol. 28, no. 3, pp. 328-340, March 1981, doi: 10.1109/T-ED.1981.20336.
    [20] S. Turuvekere, D. S. Rawal, A. DasGupta and N. DasGupta, "Evidence of Fowler–Nordheim Tunneling in Gate Leakage Current of AlGaN/GaN HEMTs at Room Temperature," in IEEE Transactions on Electron Devices, vol. 61, no. 12, pp. 4291-4294, Dec. 2014, doi: 10.1109/TED.2014.2361436.
    [21] P. E. Cottrell, R. R. Troutman, and T. H. Ning, Hot-electron emission in n-channel IGFET’s, IEEE Journal of Solid-State Circuits 14, 422 (1979)
    [22] Shankar, R. Principles of Quantum Mechanics 2nd. Kluwer Academic/Plenum Publishers. 1994.
    [23] J. L. Moll, Physics of Semiconductors (McGraw-Hill, New York, 1964)
    [24] M. Lezlinger and E. H. Snow, Fowler-Nordheim tunneling into thermally grown SiO2, Journal of Applied Physics 40, 278 (1969)
    [25] K. Kim, Technology for sub-50nm DRAM and NAND flash manufactiring, Technical Digest-International Electron Devices Meeting, 323 (2005)
    [26] J. Kim, J. M. Kim, S. H. Noh, S. L. Min and Y. Cho, A space-efficient flash translation layer for compactflash system, IEEE Transactions on Consumer Electronics 48, 366 (2002)
    [27] H. Pon, "Technology scaling impact on NOR and NAND flash memories and their applications," 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings, Shanghai, China, 2006, pp. 697-700, doi: 10.1109/ICSICT.2006.306440.
    [28] C. Lee, S. H. Baek and K. H. Park, "A Hybrid Flash File System Based on NOR and NAND Flash Memories for Embedded Devices," in IEEE Transactions on Computers, vol. 57, no. 7, pp. 1002-1008, July 2008, doi: 10.1109/TC.2008.14.
    [29] LeCun, Y., Bengio, Y. & Hinton, G. Deep learning. Nature 521, 436–444 (2015). https://doi.org/10.1038/nature14539
    [30] Shane De Silva: “The Maths behind Back Propagation”
    [31] Amir Yazdanbakhsh, Ashkan Moradifirouzabadi, Zheng Li, Mingu Kang: “Sparse Attention Acceleration with Synergistic In-Memory Pruning and On-Chip Recomputation”
    [32] Son Ngoc Truong and Kyeong-Sik Min: “New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing”
    [33] Gao, L., et al., Fully parallel write/read in resistive synaptic array for accelerating on-chip learning. Nanotechnology, 2015. 26(45): p.455204.
    [34] R. Gonzalez and M. Horowitz, "Energy dissipation in general purpose microprocessors," in IEEE Journal of Solid-State Circuits, vol. 31, no. 9, pp. 1277-1284, Sept. 1996, doi: 10.1109/4.535411.
    [35] Liang, J., et al., Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array. ACM Journal on Emerging Technologies in Computing Systems, 2013. 9(1): p. 1-14.
    [36] Sakurai, T. and K. Tamaru, Simple formulas for two- and three-dimensional capacitances. IEEE Transactions on Electron Devices, 1983. 30(2): p. 183-185.
    [37] Yu Bai, Minshuo Chen, Pan Zhou, Tuo Zhao, Jason D. Lee, Sham Kakade, Huan Wang, Caiming Xiong: “How Important is the Train-Validation Split in Meta-Learning?”
    [38] J. -N. Wu, "Compression of fully-connected layer in neural network by Kronecker product," 2016 Eighth International Conference on Advanced Computational Intelligence (ICACI), Chiang Mai, Thailand, 2016, pp. 173-179, doi: 10.1109/ICACI.2016.7449822.
    [39] Sanghyeon An, Minjun LeeAn Ensemble of Simple Convolutional Neural Network Models for MNIST Digit Recognition”
    [40] D. Baderna et al., "A 1.2 V sense amplifier for high-performance embeddable NOR flash memories," 2005 IEEE International Symposium on Circuits and Systems, Kobe, Japan, 2005, pp. 1266-1269 Vol. 2, doi: 10.1109/ISCAS.2005.1464825.
    [41] T. Ogura et al., "A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function," in IEEE Journal of Solid-State Circuits, vol. 41, no. 11, pp. 2589-2600, Nov. 2006, doi: 10.1109/JSSC.2006.883319.
    [42] B. Jacquet, F. Jamet and J. Baratgin, "On the Pragmatics of the Turing Test," 2021 International Conference on Information and Digital Technologies (IDT), Zilina, Slovakia, 2021, pp. 123-130, doi: 10.1109/IDT52577.2021.9497570.

    下載圖示
    2026-08-31公開
    QR CODE