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研究生：	林惠禎 Lim, Huey-jen
論文名稱：	具有全新低電壓電流感應放大器的低功率暫存器檔案設計 Low-Power Register File with Novel Low-Voltage Current Mode Sense Amplifier
指導教授：	邱瀝毅 Chiou, Lih-Yih
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	104
中文關鍵詞：	低功率、低電壓、電流感應放大器、暫存器檔案
外文關鍵詞：	Memory, Low voltage, Low power, Current Mode Sense Amplifier, Register File
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隨著微處理器的持續地進步，高效能低功率暫存器檔案的設計將是其中一項主要的挑戰。頻繁的資料存取已使到暫存器檔案為微處理器中主要功率消耗的來源之一，也成為微處理器中的一個過熱點。本論文利用TSMC0.18μm CMOS製程設計了一個具有一組寫入埠、兩組讀出埠、容量為32×32位元的多個操作電壓暫存器檔案。

此設計應用了低電壓操作原理，把暫存器裡的記憶體操作在0.5V，以降低功率的消耗，同時也使用了一種正向Body偏壓的技術來提高工作效能，讓此設計在摸擬時能夠達到200MHz的最高操作頻率。除此以外，也設計了一個能夠操作在bit line只有0.5V的全新低電壓電流感應放大器，此感應放大器適用於更大型的暫存器檔案設計，以達到更大的降低功率消耗的效果。摸擬結果顯示與傳統的暫存器檔案相比，本論文所提出的設計有效地把平均功率消耗降低了80%。

High-performance low-power register file design has become one of the critical conditions for the continual advancement in wide-issue and deeply pipelined superscalar microprocessors. Frequent accesses to the register file makes it one of the major sources of power consumption and one of the prime hot-spots. A novel multi-voltage register file with one write port, two read ports and 32x32 bits implemented using TSMC 0.18μm is presented in this thesis. Low voltage techniques are applied onto the register file to reduce the power consumption while having a maximum operating frequency of 200MHz during pre-simulation. A low voltage operation of 0.5V is used for the memory core with adaptive forward body biasing. A novel low-voltage current mode sense amplifier is designed to operate with the low bit-line voltage of 0.5V of which could be used for a larger register file system. Upon simulation, an average power reduction of 80% could be achieved as compare with the normal register file working at nominal voltage.

Chapter 1	..............................................1
Introduction...........................................1
1.1 Background.........................................1  
1.2 Motivation.........................................2
1.3 Contributions......................................2
1.4 Thesis Overview....................................3
Chapter 2	..............................................4
Low Power Memory Design................................4
2.1 Sources of Power Consumption in Memory.............5
2.2 Low Power Design Techniques for Memory.............7
2.3 Recent Works.......................................9
Chapter 3	.............................................12
Multi-Voltage Low Power Register File Design..........12
3.1 System Architecture Overview......................12
3.2 Memory Core.......................................16
3.3 Peripheral Circuits...............................20
Chapter 4	.............................................24
Low Voltage Multi-ports SRAM Cell Design..............24
4.1 Ultra-low Voltage Techniques......................25
4.1.1 Forward Body Biasing Technique	.................29
4.2 Operations of Multi-ports SRAM Cells..............33
4.2.1 Read Operation of SRAM Cell.....................35
4.2.2 Write Operation of SRAM Cell....................37
4.3 Low-voltage Multi-ports SRAM Cell design with FBB.38
4.4 Pre-charge circuit with FBB.......................42
Chapter 5	.............................................45
Low-Voltage Current Mode Sense Amplifier Design.......45
5.1 Current Mode V.S. Voltage Mode....................46
5.1.1 Voltage Mode Sense Amplifier....................48
5.1.2 Current Mode Sense Amplifier....................52
5.2 Related Works on Current Mode Sense Amplifier Design................................................55
5.3 Novel Low-voltage Current Mode Sense Amplifier Design................................................59
Chapter 6	.............................................63
Simulation Results....................................63
6.1 Simulation Results for Low-Voltage SRAM...........63
6.1.1 Low-Voltage SRAM without FBB....................64
6.1.2 Low-Voltage SRAM with FBB.......................67
6.1.3 Pre-charge circuit with FBB.....................68
6.2 Simulation Results for Novel Low-Voltage Current Mode Sense Amplifier.......................................70
6.3 Pre-layout Simulation for Register File...........77
6.4 Power Analysis for Register File..................82
6.5 Post-layout Simulation for Register File..........86
6.6 Layout and Chip Implementation....................95
Chapter 7	.............................................99
Conclusions and Future Works..........................99
7.1 Conclusions.......................................99
7.2 Future Works.....................................100
References...........................................101
                                    

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校內：2010-08-14公開
校外：2010-08-14公開

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