摘要

在本篇論文我們設計並實作出一個具有時脈管理系統的AMBA相容10/100/ 1000 Mbps 乙太網路媒介存取控制晶片。在本晶片與Host system的溝通介面部分，提供了與AMBA Bus system相容的匯流排介面。在對於實體層的溝通方面，則是提供同時支援MII (for 10/100 Mbps transmission speed)以及GMII(for 1000 transmission speed)兩種不同的媒體介面。我們內建了一個能夠減少能源消耗的時脈管理系統（Clock management system），時脈管理系統能依照目前的工作情形對於時脈的輸入進行管理，可以減少能源在時脈上無謂的消耗。
晶片的工作方式是依照來自於上層的要求作傳送封包的動作，透過AMBA中的資料匯流排取得要傳送的封包資料，加上CRC檢查碼後，經由MII傳送到實體層。MAC同時會監聽來自於實體層的訊息，如果有封包資料傳來，會把資料從實體層接收進來暫存在Buffer中，在經過Destination Address以CRC碼檢查無誤後，將封包資料上傳到AMBA匯流排上。在工作過程中，時脈管理系統會同時動作，進行時脈管理以達到省電的目的。
我們的Tri-speed MAC是以Verilog HDL RTL程式撰寫。並且以“Xilinx foundation series F3.1i ”實作。在驗證方面，我們提供了一個完整的MAC研發測試環境，包括Modelsim Function simulation的驗證環境以及FPGA驗證環境，並且在上述的環境中驗證成功。

Abstract

This thesis presents the design and implementation a 10/100/1000 tri-speed MAC with low power consumption for AMBA (Advanced Microcontroller bus architecture) system chip that complies with IEEE 802.3z standard. We provide AHB interface of the AMBA bus system as the communication channel between the tri-speed MAC and the host system, and a two-in-one interface of GMII and MII for physical layer devices. We have also developed a clock management module to reduce power consumption. This MAC chip achieves the goal of reducing the power consumption by controlling the clocks.

When our Tri-speed MAC works on transmission, a valid frame data from the LLC is striped and converted into a string of serial data and passed to the PHY. On receiving, the chip aggregates the serial data via Gigabit Media Independent Interface (GMII) from the Physical Layer and passes a valid frame to the Logical Link Control Layer (LLC).

The Tri-speed MAC unit is implemented in RTL codes using Verilog HDL. We implement the Tri-speed MAC with “Xilinx foundation series F3.1i”. We also provide the ModelSim function simulation environment and the FPGA simulation environment. The design is verified in ModelSim function simulation environment and an FPGA board with physical layer protocol for Ethernet compatibility.

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