一般具音頻放大器的多媒體系統如DVD播放機、電視、手提音響等產品，為達輕薄短小的設計要求，系統內部需有音頻放大器及提供放大器所需電源之電源管理等晶片。電源管理晶片中，為了提供放大器穩定的電壓，直流轉換器也被廣泛使用。為達高電源效率，D類音頻放大器已越來越受到歡迎。而直流轉換器及D類音頻放大器之內部架構均可分為脈波寬度調變控制器以及功率輸出級兩部分。本論文分別對直流轉換器的控制器、D類音頻放大器的控制器、以及輸出級均提出相關的改良設計，藉此最佳化整體系統效能。
在直流轉換器的設計上，本論文提出三種新穎設計技術。首先，一般直流轉換器被用來在較大的輸入電壓及輸出電流變動範圍下均能提供穩定的直流電源。對此大操作範圍而言，直流轉換器可藉由本論文所提出之「效率最佳化切換頻率控制」方法，來達成轉換器整體效率最佳化。此方法可由一低複雜度、低功率消耗之「效率最佳化切換頻率產生器」來實現。其次，本論文提出可重新組態之補償器，用以同時改善轉換器之負載調節率及暫態響應。最後，一種片段線性電流偵測器也被提出，用來減低控制器功率消耗並且不致於犧牲偵測之準確度。結合以上所提的三種改良設計技術，本論文也實現一個直流至直流轉換器，並以0.35μm，3.3V之互補式金氧半導體製程製作。量測結果顯示在輕載與重載條件下，功率消耗分別被節省了16mW及15mW，分別相當於16% 及1%之功率效率提升。負載調節率及暫態響應回復時間則分別被改善了40mV及12μs，而片段線性電流偵測器則節省了3mW的功率消耗。與其它已發表之0.35μm互補式金氧半導體製程所製作的轉換器相比，本文中所實現之轉換器使用了較小的晶片面積0.97mm2，卻能達到較高的轉換效率至96.3%。
隨著多媒體儲存普遍數位化且數位信號處理技術之蓬勃發展，數位輸入之D類音頻放大器也越受歡迎。對數位輸入D類放大器的脈波寬度調變控制器設計而言，積分三角調變技術被用來在較低切換頻率下達到較高之解析度。增加積分三角調變器之最大穩定輸入振幅可使D類放大器的低失真輸出功率範圍增加。本論文在積分三角調變器架構選擇建議兩種方式以獲得較大的穩定輸入振幅。此外，尚可藉由迴路濾波器的設計來提高穩定輸入振幅。先前文獻已知採用根軌跡於單位圓內之設計方法可使積分三角調變器達到全額穩定輸入振幅。但該方法採用了較為保守的迴路傳輸函數而導致信號雜訊比較低。本文將迴路傳輸函數的極零點位置最佳化，使得利用根軌跡於單位圓內所設計的積分三角調變器之信號雜訊比可被極大化。根據所提的方法，最佳化的3階及4階調變器以被設計出來，並且歸納出一個系統化的方法來設計更高階的調變器。在超取樣比為32、6位元量化器情況下，一個4階根軌跡於單位圓內之積分三角調變器可達到最高信號雜訊比為109分貝。與先前已發表設計方法相比，信號雜訊比提高了20分貝。為了論證此種根軌跡於單位圓內之積分三角調變器的優點，我們舉出一個將其用於D類放大器的應用例。此D類放大器之低失真輸出功率範圍在相同電源下可被極大化。
在D類放大器輸出級的設計方面，本論文量化分析了由輸出級雜散電阻所造成的諧波失真。此分析結果之理論值與SPICE驗證結果相符。利用此結果，在D類放大器輸出級設計上可使成本及效能間達到較佳的權衡。

To achieve the design target of light-weight and miniaturized-volume, power management and audio amplifier ICs are required for general multimedia systems with audio amplifiers, such as DVD players, televisions, and boom-box products. For the power management, DC-DC converters are widely used to provide a stable supply voltage for amplifier ICs. For the audio amplifier, class-D audio amplifiers have become increasingly popular due to their high efficiency. Both the DC-DC converter and the class-D audio amplifier can be divided into the pulse-width modulation (PWM) controller and the power output stage. In this dissertation, new techniques for the controller of DC-DC converters, the controller of class-D amplifiers, and the output stage are proposed to improve the performance of the whole system.
For DC-DC converter design, three new design techniques are proposed. Firstly, large input voltage range and wide output current range are usually needed for DC-DC converters. For these input and output conditions, the converter’s efficiency can be maximized by a proposed Efficiency-Optimized Frequency (EOF) control. The optimal switching frequency for maximizing the efficiency is generated by a low-complexity and low-power EOF generator. Secondly, a reconfigurable compensator is developed for improving the load regulation and the transient response. Lastly, a Piecewise-Linear Current Sensor (PLCS) is employed to reduce controller power loss without sacrificing the sensing accuracy. With the above three proposed methods, a monolithic current-mode DC-DC buck converter is implemented in a 0.35μm 3.3V CMOS process. The measured power-loss reductions and efficiency improvements achieve 16mW and 15mW, and 16% and 1%, both in light and heavy loads, respectively. The load regulation and the transient recovery time are improved by 40mV and 12μs, respectively, while the PLCS can reduce 3mW of power loss. Compared with other published converters in 0.35μm CMOS process, the implemented converter achieves a higher efficiency of 96.3% and smaller chip area of 0.97mm2.
Widespread digital audio sources and mature digital signal processing (DSP) techniques drive the necessity of using a digital-input interface. Digital-in class-D amplifiers are thus more and more popular. For digital-in class-D amplifiers, delta-sigma modulators (DSMs) are employed to obtain higher resolution with a low PWM frequency. By increasing the maximum stable input range (Xinmax) of the DSM, the low-distortion output power of an audio amplifier can be enlarged. In this dissertation, two system-level design considerations for the DSM design are addressed to increase Xinmax. In addition, Xinmax can be increased by improving the loop-filter design. Single-stage high-order DSMs designed by root locus inside unit circle (RLiUC) methods can operate stably with full-scale input. The previously-published RLiUC method uses a conservative approach to design the loop filter’s transfer function H(z) of a DSM, thus resulting in a modest signal-to-noise ratio (SNR). In this dissertation, the pole-zero locations of H(z) are optimized to maximize the SNRs. Accordingly, optimal 3rd- and 4th-order RLiUC DSMs are designed and a systematic method for orders higher than 4 is developed. With an oversampling ratio of 32 and a quantizer bit number of 6, the optimized 4th-order RLiUC DSM achieves a peak SNR of 109dB. Compared with the previously-published result, the SNR is improved by 20dB. To demonstrate the advantage of RLiUC DSMs, an application example for a class-D amplifier is used. With the RLiUC DSM, the achieved low-distortion output power of class-D amplifiers can be maximized.
For the output stage design, distortion caused by parasitic resistances of the power stage is analyzed, the results of which are well-matched with SPICE verifications. By employing the results, a better compromise between cost and performance can be obtained.

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