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研究生： 盧泰樺
Lu, Tai-Hua
論文名稱： 管線化處理器核心測試程式發展與其錯誤涵蓋率評估方法之研究
Development of Efficient Test Programs and Fault Coverage Evaluation Methods for Pipeline Processor Cores
指導教授： 陳中和
Chen, Chung-Ho
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 87
中文關鍵詞： 軟體自我測試 、管線化處理器測試 、確定性的軟體自我測試 、隨機性的軟體自我測試 、混合式軟體自我測試 、錯誤涵蓋率評估 、錯誤觀察方法
外文關鍵詞： Software-based self-testing (SBST), Pipeline processor testing, Deterministic SBST, Random SBST, Hybrid SBST, fault coverage measure, Fault observation method
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    • 測試系統晶片中的嵌入式處理器，軟體自我測試是一種大有可為的方法。然而達到高錯誤涵蓋率仍是軟體自我測試方法的挑戰。對此挑戰，本篇論文提出可結合多層次抽象化的軟體自我測試方法的高效率程式區塊軟體自我測試方法與其兩者的混和式軟體測試方法。多層級抽象化的軟體自我測試方法使用了邏輯閘層與架構層的資訊來改善結構性錯誤的涵蓋率，使用ATPG軟體產生限制性的測試樣本去有效的測試基本IP，並且參考暫存器傳輸層與架構層來發展剩下的控制邏輯電路的測試程式。而高效率程式區塊為基礎的軟體自我測試方法包含了依序區塊、亂序區塊、返回區塊、與觸發例外/中斷要求的指令流。為了改善結構性錯誤涵蓋率，這些區塊的建立參考了微處理器架構與指令集架構的資訊。最後，為了實現最高錯誤涵蓋率，我們將上述的兩者方法結合成混合式軟體自我測試方法。由於這種結合的混合測試程式的互補性，它可以實現處理器的錯誤涵蓋率的效果相媲美與傳統掃描鏈的方法。本文對測試反應的觀察方法其錯誤覆蓋率的影響也進行了研究。我們提出宏觀觀察與微觀觀測的觀察方法模型，研究顯示使用軟體自我測試的最有效的觀察方法是通過多重輸入簽名暫存器直接連接處理器的內部匯流排，而只有觀察記憶體內的程式測試結果將導致處理器錯誤涵蓋率的降低。

    Software-based self-test (SBST) is a promising approach for testing a processor core embedded in an SoC system; however, to achieve high processor fault coverage is a great challenge in SBST methodologies. To tackle this challenge, an effective program-block based random SBST and its hybrid SBST which combines with a multiple-level abstraction based deterministic SBST (MLA-SBST) for pipeline processor cores are presented. The MLA-SBST methodology uses gate-level and architecture information to improve coverage for structural faults. This SBST methodology uses an automatic test pattern generation (ATPG) tool to generate the constrained test patterns to effectively test the combinational fundamental IPs used in the processor. The approach refers to the register transfer level (RTL) code and processor architecture for the test of the control and steering logic in test routine development. The effective program-block based SBST consists of a combination of in-order blocks, out-of-order blocks, return blocks, as well as instruction sequences to trigger exception/interrupt requests. To improve fault coverage, the development of these blocks also refers to the instruction set architecture and processor architecture. Finally, we present a hybrid SBST which combines the MLA-SBST with the program-block based SBST for higher fault coverage. Due to the complementary nature of this hybrid test program, it can achieve processor fault coverage that is comparable to the performance of the conventional scan chain method. The test response observation methods and their impacts on processor fault coverage are also investigated. We present the concept of micro observation versus macro observation and show that the most effective method of using SBST is through a multiple input signature register connected to the processor local bus, while conventional methods that only observe the program results in the memory lead to significantly less processor fault coverage.

    摘 要 I ABSTRACT II 誌 謝 IV TABLE OF CONTENTS V LIST OF TABLES IX LIST OF FIGURES X CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 INTRODUCTION TO THE PROPOSED METHODS 2 1.3 CONTRIBUTIONS 4 1.4 ORGANIZATION OF THESIS 5 CHAPTER 2 BACKGROUND AND PREVIOUS WORK 7 2.1 BACKGROUND 7 2.2 PREVIOUS WORK 8 2.3 OVERVIEW OF TARGET PROCESSORS 11 CHAPTER 3 FAULT OBSERVATION AND FAULT COVERAGE ESTIMATION 15 3.1 CONCEPT 15 3.2 FAULT OBSERVATION METHODS 17 3.2.1 MICRO OBSERVATION METHOD - MISR 17 3.2.2 MACRO OBSERVATION METHOD 18 3.2.2.1 SPACIAL AND TEMPORAL RELATIONSHIPS 20 3.2.2.2 UNCERTAIN RELATIONSHIP 22 3.3 FAULT OBSERVATION MECHANISMS 23 3.3.1 CONTROL SIGNAL OF MASK CIRCUIT FOR MACRO OBSERVATION MECHANISMS 26 3.4 SUMMARY 26 CHAPTER 4 DETERMINISTIC SBST METHODOLOGY WITH MULTIPLE LEVEL ABSTRACTION 28 4.1 CONCEPT 28 4.2 PROCESSOR PART CLASSIFICATION BASED ON MULTIPLE-LEVEL ABSTRACTION 29 4.2.1 INSTRUCTION SET ARCHITECTURE REGISTER 30 4.2.2 FUNDAMENTAL IP 31 4.2.3 CONTROL, STEERING LOGIC, AND PIPELINE REGISTERS 31 4.2.4 PIPELINE-RELATED CONTROL LOGIC 32 4.3 TEST ROUTINE DEVELOPMENT 32 4.3.1 TEST ROUTINE DEVELOPMENT FOR INSTRUCTION SET ARCHITECTURE(ISA) REGISTER 32 4.3.2 TEST ROUTINE DEVELOPMENT FOR FUNDAMENTAL IP 35 4.3.2.1 CONSTRAINT SETTING 36 4.3.2.2 TEST ROUTINE DEVELOPMENT FOR DATA PROCESSING IP 37 4.3.2.3 TEST ROUTINE DEVELOPMENT FOR DATA MEMORY ADDRESS MANIPULATION IP 37 4.3.2.4 TEST ROUTINE DEVELOPMENT FOR INSTRUCTION MEMORY ADDRESS MANIPULATION IP 38 4.3.3 TEST ROUTINE DEVELOPMENT FOR CONTROL, STEERING LOGIC, AND PIPELINE REGISTERS 39 4.3.4 TEST ROUTINE DEVELOPMENT FOR PIPELINE-RELATED CONTROL REGISTERS 40 4.3.4.1 TEST ROUTINE DEVELOPMENT FOR HAZARD DETECTION LOGIC 40 4.3.4.2 TEST ROUTINE DEVELOPMENT FOR PIPELINE FORWARDING MECHANISM 42 4.4 SUMMARY 43 CHAPTER 5 RANDOM SBST METHODOLOGY USING EFFECTIVE PROGRAM BLOCKS 44 5.1 CONCEPT 44 5.2 ORGANIZATION OF BLOCKS 46 5.2.1 IN-ORDER BLOCK 47 5.2.2 OUT-ORDER BLOCK 48 5.2.3 RETURN BLOCK 48 5.2.4 REGISTER FILE TEST 49 5.2.5 CONTROL AND DATA PATH TEST 50 5.2.6 FORWARDING TEST 51 5.2.7 EXCEPTION/INTERRUPT TESTING 53 5.3 ISSUE OF THE RANDOM SBST METHOD 54 5.3.1 TEST SHELL MECHANISM 54 5.3.1.1 THE ARCHITECTURE OF THE TEST SHELL 55 5.3.1.2 MULTIPLEXERS 56 5.3.1.3 DATA ADDRESS MASK 57 5.3.1.4 TEST CONTROLLER 58 5.3.2 MMU FOR TESTING MECHANISM 59 5.4 SUMMARY 60 CHAPTER 6 EXPERIMENTAL RESULTS 61 6.1 THE FLOW OF FAULT SIMULATION 61 6.2 SYNTHESIS CASE 1: 0.35UM, 50MHZ 62 6.3 SYNTHESIS CASE 2: 0.18UM, 125MHZ 65 6.4 RESULT DISCUSSIONS 67 6.5 EFFECTIVENESS OF VARIOUS PROGRAM BLOCKS 68 6.6 DIFFERENCE BETWEEN TEST SHELL MECHANISM AND MMU FOR TESTING MECHANISM 69 6.7 DISCUSSION ON OPTIMISTIC MACRO OBSERVATION METHOD AND PESSIMISTIC MACRO OBSERVATION MEHTOD 70 6.8 IMPACT OF RANDOM TEST PROGRAM SIZE AND OBSERVATION METHODS 71 6.9 ON THE TESTING OF EXCEPTIONS AND INTERRUPTS 73 6.10 APPLICATION AND LIMITATION 74 6.11 COMPARISONS WITH OTHER WORKS 75 6.12 SUMMARY 77 CHAPTER 7 CONCLUSIONS AND FUTURE WORK 78 7.1 CONCLUSIONS 78 7.2 FUTURE WORK 80 REFERENCES 81 PUBLICATIONS 86 VITA 87

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