| 研究生: |
張永謙 Chang, Yung-Chien |
|---|---|
| 論文名稱: |
預測式數位電流控制降壓型轉換器研究與設計 Study and Design of Predictive Digital Current Controlled Buck Converter |
| 指導教授: |
蔡建泓
Tsai, Chien-Hung |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2014 |
| 畢業學年度: | 102 |
| 語文別: | 中文 |
| 論文頁數: | 117 |
| 中文關鍵詞: | 預測式 、數位電流模式 、降壓 、責任週期校正 、一個切換週期延遲 |
| 外文關鍵詞: | predictive, digital current mode control, buck, duty calibration technique, one cycle |
| 相關次數: | 點閱:117 下載:7 |
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本論文首先實現了數位預測式平均電流控制降壓型轉換器。不同於傳統數位電流控制需要使用高取樣頻率及高解析度來取樣變動劇烈的電感電流資訊,本架構電流迴路所使用之ADC(Current ADC)僅需和切換頻率相同即可,此外還能以低解析度實現來降低此ADC的功耗及成本。經由預測式控制理論雖然能夠知道電流迴路能夠延遲一個切換週期就能回穩,但實際上卻會受到系統延遲的影響,導致電流迴路產生誤差而使電流的暫態響應變差。因此本文針對此問題提出了“責任週期校正技術”克服系統延遲來改善電流迴路的暫態響應和系統暫態表現,最後經由此系統在FPGA實現而得到的量測結果可知,加入此技術確實能夠實現一個週期延遲的電流迴路暫態響應及改善系統暫態表現。此外為了縮短此系統在設計上的時間,本文也將本實驗室先前所開發之數位電壓模式控制補償器設計自動化平台作驗證後,將其擴充至預測式數位電流控制架構以供使用。
In this thesis, a predictive digital current mode controlled buck converter is presented. Unlike traditional digital current mode control which needs to sample the rapidly-changed inductor current information with high frequency and resolution ADC. The frequency in this structure is as low as switching frequcncy. Furthermore, it can be implemented with low resolution to reduce cost and power consumption. Theoretically, predictive current mode control loop let the inductor current track the current command with one cycle delay, the system delay resulted from ADC conversion and compensator calculation would cause the current-loop response to become slower and thus have worse transient performance. In order to improve the current-loop response to reach one-cycle delay, this work proposes a duty calibration technique for predictive digital average current mode controlled buck converter. Experimental results from FPGA prove that the technique for one-cycle delay is feasible and improving the transient performance. Besides, the earlier developed compensator design automation GUI(Graphical User Interface) tool for digital voltage mode is extended to predictive current mode structure, simplifing complicated compensator design flow and reducing the time-to-implementation.
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