浮點數算數運算比起整數運算是較為複雜且難以用硬體實現，尤其是所使用的演算法會影響精準度、面積、速度、功耗。本論文提出基於IEEE 754標準的高精準度、低面積、快速運算的浮點數算數運算單元。我們探討牛頓逼近法(Newton-Raphson method)及泰勒級數展開式(Taylor series expansion method)計算浮點數算數函數，比較牛頓逼近法的迭代次數及泰勒級數展開式的階數所能達到的精準度及運算所花費的時間。此外，演算法使用查找表(Look Up Table, LUT)並利用Lloyd-Max 量化器降低查找表的尺寸且保持最佳的精準度。此浮點數算數運算單元使用VerilogHDL在TSMC 180nm製程下合成並模擬驗證。

This paper proposes a high speed and small area design of an IEEE-754 Floating-Point Process Unit (FPU) for GPU. We analyze the orders of Taylor series expansion and Lookup Table (LUT) to ensure less execution time. In addition, we use Lloyed-Max quantizer in Lookup Table to keep sizes of tables being only 56.902 Kbytes and keep high accuracy on our algorithms. The hardware uses pipeline architecture to improve throughput. It is modeled in VerilogHDL and synthesized in 180nm CMOS technology after verification. The simulation results of the proposed FPU demonstrates the frequency can reach 102MHz.

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