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研究生：	樊冠緯 Fan, Kuan-Wei
論文名稱：	根據系統層級設計之有效率且低成本的H.264位元率控制機制 Cost-Effective Rate Control Scheme for H.264/AVC by System-Level Design
指導教授：	郭致宏 Kuo, Chih-Hung
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	135
中文關鍵詞：	視訊編碼、位元控制、系統層級設計
外文關鍵詞：	rate control, video codng, system-level design
相關次數：	點閱：46 下載：2
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本論文以系統設計層級的角度去思考並提出一個低成本且低複雜度的位元控制機制，此機制不像其他位元控制演算法專注於位元失真效能(rate-distortion performance)上，而忽略在軟體或硬體實現的複雜度以及整體系統實現後的效能表現。首先，我們提出一個低成本且低複雜度的位元控制機制，再評估位元控制演算法和系統架構的相互關係，提出一個適合於嵌入式系統實現的位元控制機制和其軟硬體切割方式。此方法將所提之有效率且低成本的區塊層級位元控制 (MB layer rate control) 演算法實現在硬體上，並且和實現在系統CPU上的典型畫面層級位元控制(frame layer rate control) 演算法共同完成位元控制的功能。我們提出之位元控制機制的複雜度比H.264的區塊層級位元控制簡單，並且實驗結果顯示：我們的機制比H.264的畫面層級位元控制演算法有較少的位元波動情況(rate fluctuation)，並且和H.264的區塊層級位元控制有相近的效能，例如：位元波動情況、目標位元率錯誤 (target bit rate mismatch) 和位元失真效能。

This thesis presents a low cost and low complexity rate control scheme based on system-level design. Conventional rate control algorithms only focus on rate-distortion performance and did not consider their performance and complexity when implementing on an embedded system. Our proposed rate control scheme jointly considers the performance and its related architecture for hardware/software co-design. The proposed cost-effective macro-block (MB) layer rate control module works in hardware, and the typical frame layer rate control is executed in system CPU. It is less complex than the rate control module adopted by H.264 JM13.2 reference software and is more suitable for SoC system implementation. The experimental results show that the rate control ability of our proposed is better than H.264 frame layer rate control. Even if compared with MB layer rate control in H.264, the performance is almost similar.

口試合格證明………………………………………………………………I
中文摘要……………………………………………………………………II
ABSTRACT…………………………………………………………………III
致謝…………………………………………………………………………IV
LIST OF FIGURES …………………………………………………………VII
LIST OF TABLES  …………………………………………………………IX
Chapter 1 Introduction…………………………………………………………1
1.1 Introduction to rate control …………………………………………………1
1.1.1 VBR ……………………………………………………………………3
1.1.2 CBR ……………………………………………………………………3
1.2 Research motivation ………………………………………………………4
1.3 Organization of thesis………………………………………………………5
Chapter 2 Research Background  ………………………………………………6
2.1 Overview of software-based rate control ……………………………………6
2.1.1 Rate Allocation ……………………………………………………………8
2.1.2 Rate-distortion (R-D) model and its updating method………………………10
A. Quadratic rate-distortion model and its update …………………………………10
B. Linear rate-distortion model and its update ……………………………………12
C. ρ domain R-D model………………………………………………………12
2.1.3 Linear MAD prediction ………………………………………………13
2.2 Rate control for hardware encoder ……………………………………14
2.2.1 Rate control of hardware implementation …………………………15
2.2.2 Rate control of software implementation …………………………15 
Chapter 3 Proposed Rate Control Scheme ………………………………………17 
3.1 The interaction between algorithm and system architecture…………17
3.1.1 The analysis of rate control in MB layer and frame layer ………17
3.1.2 The analysis of rate control in system architecture  ……………19
3.1.3 Proposed hardware/software partition of rate control ……………20
3.2 Overview of proposed rate control…………………………………………21
3.3 Rate control parameter adjustment…………………………………………26
3.4 Proposed frame level MAD prediction………………………………………28
3.5 Proposed MB level MAD prediction …………………………………………33
3.6 QP adapter ………………………………………………………………………41
3.7 QP decision  ……………………………………………………………………45
3.8 Algorithm computational complexity evaluation…………………………45
3.9 Summary  …………………………………………………………………………49
Chapter4 Proposed Scheme with Data Dependency Consideration……………50
4.1 Data dependency of MB-pipeline hardware encoder………………………50
4.2 MB level MAD prediction with data dependency consideration  …52
4.3 QP adapter with data dependency consideration …………………56
4.4 The evaluation of different coding flow in H.264/AVC ………………59
4.5 Summary ………………………………………………………………64
Chapter 5 Experimental Results …………………………………………67
Chapter 6 Conclusion and Future Work …………………………………85
Reference ……………………………………………………………………87
Appendix A……………………………………………………………………91
Appendix B……………………………………………………………………100
Appendix C……………………………………………………………………109
                                    

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校內：2010-08-19公開
校外：2010-08-19公開

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