對嵌入式處理器而言，指令快取記憶體所耗用的能量佔整體處理器相當的比例，因此如何藉由改善指令遞送過程的能量效率，進而達成省電的目標，也就成為嵌入式系統的重要課題。本論文首先探討諸多改善指令遞送過程所耗用成本的方案，並進而提出一個稱為指令歷程再利用的架構，來改善嵌入式處理器在遞送指令時耗用的能源效率，同時增進效能。藉由一個稱為歷程快取記憶體的簡單硬體結構，我們提出的方案可以在管線的尾端將執行完畢的指令收集起來，並保持不同指令間前後的順序關係，也就是執行的歷程，進而在必要的時候重複利用這些已經出現過的歷程，達到同時提高能源效率和執行效能的雙重目標。根據實驗結果，對於一個內建16KB指令快取記憶體的嵌入式處理器，增設2048個指令的歷程快取記憶體之後，可以提高21%的IPC效能同時降低75%指令快取記憶體所耗用的能量。本文所提出的歷程快取方案還包括了另一項特色，就是使系統對於傳統記憶體快取的依賴度大幅的降低。增設了歷程快取記憶體的系統只需要不到一半的傳統指令快取記憶體，就能達到同水準的執行效能。這樣的特色提供了嵌入式系統設計者們一個新的選擇，也就是透過整合本文所提出的歷程快取記憶體，設計者將有機會將傳統快取記憶體所佔用的面積和功率縮小，用以換取更大的設計彈性。

For an embedded processor, the efficiency of instruction delivery has attracted much attention since instruction cache accesses consume a great portion of the whole processor power dissipation. In this thesis, the previous works related to instruction delivery are explored, and a novel scheme called Trace Reuse Cache (TR cache) architecture is proposed to serve as an alternative option for energy-efficient instruction delivery. Through an effective mechanism to reuse the retired instructions from the pipeline back-end of the processor, the TR cache presents improvement both in performance and power efficiency. Experimental results show that a 2048-entry TR cache is able to provide 75% energy saving for an instruction cache of 16KB, at the same time boosts the IPC up to 21%. The scalability of the TR cache is also demonstrated with the estimated area usage and energy-delay product. The results of our evaluation indicate that the TR cache outperforms the traditional filter cache under all configurations of the reduced cache sizes. The TR cache exhibits strong tolerance to the IPC degradation induced by smaller instruction caches, thus makes it an ideal design option for the cases of trading cache size for better energy and area efficiency.

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