隨著多媒體資訊的快速發展，對於數位訊號處理器(Digital Signal Processor, DSP)的需求也日益增加。如何確保數位訊號處理器的功能正常則是個重要的議題。製造測試為晶片下線後的重要環節，對晶片功能是否正常做最後的把關。傳統的Scan-based與BIST的測試方案，都需要內建測試電路來進行測試工作，對此將造成整體面積的增加。而軟體式自我測試方案(Software-Based Self-Testing, SBST)則不需增加額外的測試電路，且有助於電路最佳化的設計，同時也能夠讓處理器正常執行速度(at-speed)下進行測試。

本篇論文提出一套混合式軟體自我測試方案(SBST)，並對管線設計的DSP進行測試。而測試程式的開發則結合隨機性(Random)與自定性(Deterministic)兩種測試方案，來達到較高的錯誤涵蓋率(Fault coverage)。隨機測試程式的發展是透過硬體架構與指令集的分析，並建構Basic block作為隨機測試程式的發展基礎，以隨機方式產生不同資料路徑的指令來測試DSP的線路錯誤。而自定性測試程式的發展則是透過強迫式的錯誤資訊傳遞方法，讓有條件限制的ATPG(Automatic test pattern generation)所產生的測試向量能夠有效率的執行。最後將本篇論文所提出的混合式軟體自我測試方法實現於DSP的測試，可達到95.46%的錯誤涵蓋率。

With the highly developed multimedia information, the demand for Digital Signal Processor (DSP) is increasing. How to test the correctness of the functions of a DSP chip becomes an important issue. Manufacturing test for the functionality of the chip is an important stage after the tape-out of the chip. Both traditional scan-based and built-in self-testing (BIST) testing methodologies require built-in testing circuit to support testing procedure, which leads to an increase in overall area. However, software-based self-testing (SBST) not only needs no additional testing circuits, but also is helpful for optimizing the circuit design and allows the testing to be performed at the normal processor execution speed.

In this thesis, we propose a hybrid SBST methodology, and apply it to test a pipeline DSP. The development of test program combines both random and deterministic schemes to achieve high fault coverage. The random test program is developed by analyzing the hardware architecture and the instruction set, and by building basic blocks as the basis of the random testing program. The deterministic test program is developed by forcing fault propagation, so that the constrained test vectors generated by the ATPG tool can be executed efficiently. Furthermore, the hybrid SBST we propose is applied to DSP processors and has achieved 95.46% in processor core fault coverage.

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