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研究生: 曾文傑
Tseng, Wen-Chieh
論文名稱: 應用於多格式音訊編解碼器中分析與合成濾波器組之共架構設計
A Unified Architecture Design of Analysis and Synthesis Filterbanks in Multi-Standard Audio Codecs
指導教授: 雷曉方
Lei, Sheau-Fang
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 中文
論文頁數: 121
中文關鍵詞: 遞迴式離散餘弦轉換修正型離散餘弦正/逆轉換分析/合成正交鏡像濾波器組多格式音訊編解碼器
外文關鍵詞: Recursive, DCT, MDCT/IMDCT, AQMF/ SQMF, Multi-Standard, Audio Codec
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  • 本篇論文提出一個以遞迴式離散餘弦第四型轉換(DCT-IV)為核心來實現修正型正、逆離散餘弦轉換(MDCT / IMDCT )的快速演算法,並應用於各種音訊壓縮技術中的分析與合成濾波器組(Analysis and Synthesis Filter Banks)。該處理器可支援MP3、AAC、AAC in DRM、AAC in DAB、AC-3、TwinVQ、Ogg等多格式之共架構,除此之外,針對HE-AAC音訊規格,還能支援高品質頻帶複製技術(HQ-SBR)與低功率頻帶複製技術(LP-SBR)中分析正交鏡像濾波器組(AQMF)與合成正交鏡像濾波器組(SQMF)的運算。
    此架構透過前、後處理將MDCT/IMDCT/AQMF/SQMF運算轉化成共用的DCT-IV型式,再將一維DCT-IV分別拆解成DCT-III與DCT-II運算的二維型式演算法,藉此來提升遞迴架構的硬體效能,與近期Li et al.所發展的新式演算法相比,其整體運算週期為我們的7.5倍,而乘法運算量為我們的4.2倍,加法運算量為我們的3.1倍,係數需求量為我們的54.1倍。
    在硬體實現上,所提之電路架構僅需8個乘法器與10個加法器,我們以Altera-based platform來實現所設計之架構,其操作頻率最高為41MHz,適合應用於支援多格式的音訊編解碼器。

    This thesis proposes a fast MDCT / IMDCT algorithm whose kernel is adopted the recursive DCT-IV. It applies for analysis and synthesis filterbanks in audio codecs. This proposed design is supporting multi-standards, such as MP3、AAC、AAC in DRM、AAC in DAB、AC-3、TwinVQ、Ogg etc. Furthermore, this architecture can compute AQMF/SQMF in HQ-SBR and LP-SBR for HE-AAC.
    To implement the unified architecture design of analysis and synthesis filterbanks, MDCT/IMDCT/AQMF/SQMF are converted to DCT-IV by pre-processing and post- processing. Moreover, in order to improve performance of recursive DCT-IV, we decompose the one-dimensional DCT-IV to two-dimensional algorithm by DCT-III and DCT-II. Compare with the latest algorithm proposed by Li et al, whose computing cycle is 7.5 times than proposed algorithm, Multiplication is 4.2 times, addition is 3.1 times and coefficient requirment is 54.1 times.
    This proposed design only costs 8 Multiplier and 10 Adder for implementation. It is implemented by using Altera-based platform, and max clock rate is 41MHz. The design is suitable for multi-standard audio codecs.

    摘要.......................................................I ABSTRACT.................................................III 誌謝......................................................IV 第一章 緒論.................................................1 1.1 研究背景與動機...........................................1 1.2 各演算法簡介.............................................4 1.3 章節組織................................................6 第二章 音訊編解碼器概述........................................7 2.1 MP3簡介................................................7 2.2 AAC簡介................................................8 2.3 TwinVQ簡介............................................12 2.4 AC-3簡介..............................................14 2.5 Ogg簡介...............................................15 第三章 現有 Recursive MDCT/IMDCT 演算法分析及討論.............17 3.1 Chen et al. 演算法[16]................................17 3.1.1 RMDCT推導...........................................17 3.1.2 RIMDCT推導..........................................23 3.2 Lai et al.演算法[23]...................................30 3.2.1以IDCT-II為核心,N/4點的MDCT演算法......................30 3.2.2以IDCT-II為核心,N/8點的MDCT演算法......................34 3.3 Li et al. 演算法[24]..................................39 第四章 以DCT快速演算法實現AQMF/SQMF..........................48 4.1以DCT-IV實現複數型AQMF/SQMF.[26].........................48 4.2以DCT-II、DCT-III實現實數型AQMF/SQMF[25].................52 第五章 提出之新式多計算週期快速MDCT/IMDCT演算法.................58 5.1以DCT-IV實現MDCT/IMDCT ..................................59 5.2核心快速DCT-IV演算法與管線化加速...........................60 5.2.1 核心快速DCT-IV演算法..................................60 5.2.2 管線化加速...........................................67 5.3 DCT-III/DST-III快速演算法與硬體架構設計...................70 5.4 DCT-II/DST-II快速演算法與硬體架構設計.....................76 5.5中間級硬體架構設計........................................82 5.5.1 Cosine與Sine因子係數產生器.............................82 5.5.2 Cosine與Sine因子之乘加運算與資料摺疊處理.................87 5.5.3 硬體共用架構設計.......................................90 5.6硬體動作方式與週期數評估...................................97 第六章 比較分析與硬體實現....................................100 6.1計算週期數.............................................100 6.2運算複雜度分析..........................................103 6.3係數需求分析............................................109 6.4硬體需求分析............................................112 6.5精確度分析與硬體實現.....................................115 第七章 結論與未來發展.......................................117 參考文獻..................................................118

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