| 研究生: |
黃家偉 Huang, Chia-Wei |
|---|---|
| 論文名稱: |
應用於H.264/AVC的平行處理式解方塊濾波器 A Parallel Processing Deblocking Filter in H.264/AVC |
| 指導教授: |
賴源泰
Lai, Yen-Tai |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2011 |
| 畢業學年度: | 99 |
| 語文別: | 英文 |
| 論文頁數: | 56 |
| 中文關鍵詞: | H.264/AVC 、方塊效應 、解方塊濾波器 |
| 外文關鍵詞: | H.264/AVC, Blocking Artifact, Deblocking Filter |
| 相關次數: | 點閱:108 下載:0 |
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由於網路的迅速發展,視訊多媒體在日常生活中已經扮演著人們不可或缺的重要角色。H.264/AVC是新一代的動態影像壓縮標準,與過去的其他標準相比,他有著較高的壓縮效率,但這也使得他的運算複雜度比過去的標準要來的高。
在影像壓縮的過程當中,往往會出現影像失真的現象,而在H.264最明顯見到的現象為方塊效應,為了減少方塊效應的產生,H.264便在解碼迴圈當中採用了解方塊濾波器做為他的主要方塊,進而增加影像的品質。
在本論文中,我們提出了平行處理式的解方塊濾波器架構,和傳統的解方塊濾波器相比,不但可以用較少的時脈處理完一個巨方塊,由於資料重複使用的特性,也可以有效地降低記憶體需求。在本架構中,我們只需要160個時脈循環去處理一個巨方塊,並且在合成數據中,僅需要11.89K個邏輯閘。
Due to the rapid spread of Internet, multimedia plays an important role in daily life. H.264/AVC is a newly video compression standard, compared with the past standards, it has high compression efficiency, but also makes its high computational complexity.
In the image compression process, the image always have a problem with distortion, and the most obvious phenomenon in the H.264 is the blocking artifact, in order to reduce the blocking artifact, H.264 adapted the deblocking filter as its main block in the decoder loop, it helps to increase the image quality.
In this thesis, we proposed the parallel processing deblocking filter architecture, compared to the traditional deblocking filter, it cost less clock cycles processing a maroblock, and moreover, due to the data reuse, it reduces the memory requirement effectively. We need only 160 cycles to process a macroblock, and 11.89K gate counts needed.
[1] “Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification (ITU-T Rec. H.264|ISO/IEC 14496-10 AVC) ,” JVT-G050, 2003
[2] Gary J. Sullivan, Pankaj Topiwala, and Ajay Luthra, “The H.264/AVC Advanced Video Coding Standard: Overview and Introduction to the Fidelity Range Extensions,” Conference on Applications of Digital Image Processing, SPIE, 2004
[3] P. List, A. Joch, J. Lainema, G. Bjntegarrd, and M. Karczewicz, “Adaptive Deblocking Filter,” IEEE Transactions on Circuits and Systems for Video Technology, 2003
[4] Chao-Chung Cheng, Tian-Sheuan Chang, Member, IEEE, and Kun-Bin Lee, “An In-Place Architecture for The Deblocking Filter in H.264/AVC,” IEEE Transactions on Circuits and Systems, 2006
[5] Mehdi Jafari, Shohreh Kasaei, “Fast Intra-Prediction Mode Decision in H.264 Advanced Video Coding,” IEEE Singapore International Conference on Communication Systems, 2006
[6] Iain E. G. Richardson, “H.264 and MPEG-4 Video Compression,” UK: John Wiley & Sons, 2003.
[7] V. Bhaskaran and K. Konstantinides, “Image and Video Compression Standards: Algorithms and Architectures,” Boston, MA: Kluwer Academic, 1997.
[8] J. Ostermann, J. Bormans, P. List, D. Marpe, M. Narroschke, F. Pereira, T. Stockhammer, and T. Wedi, “Video coding with H.264/AVC: tools, performance, and complexity,” IEEE Circuit and Systems Magazine, First quarter 2004.
[9] Thomas Wiegand, Gary J. Sullivan, Gisle Bjontegaard, and Ajay Luthra, “Overview of the H.264 / AVC Video Coding Standard,” IEEE Transactions on Circuits And Systems For Video Technology, 2003.
[10] “Emerging H.264 Standard: Overview and TMS320C64x Digital Media Platform Implementation,” White Paper, 2002
[11] Ralf Schafer, Thomas Wiegand and Heiko Schwarz, “The emerging H.264/AVC standard,” EBU Technical Review, 2003
[12] Y. W. Huang, T. W. Chen, B. Y. Hsieh, T. C. Wang, T. H. Chang, and L. G. Chen, “Architecture Design for Deblocking Filter in H.264/JVT/AVC,” IEEE International Conference on Multimedia and Expo, 2003
[13] B. Sheng, W. Gao, and D. Wu, “An Implemented Architecture of Deblocking Filter for H.264/AVC,” IEEE International Conference on Image Processing, 2004
[14] M. Parlak and I. Hamzaoglu, “Low Power H.264 Deblocking Filter Hardware Implementations,” IEEE Transactions on Consumer Electronics, 2008
[15] G. Khurana, A. A. Kassim, T. P. Chua, Bi Mi M., “A Pipelined Hardware Implementation of In-loop Deblocking Filter in H.264/AVC,” IEEE Transactions on Consumer Electronics, 2006
[16] K. Xu and C. S. Choy, “A Five-Stage Pipeline, 204 Cycles/MB, Single-Port SRAM-Based Deblocking Filter for H.264/AVC,” IEEE Transactions on Circuits and Systems for Video Technology, 2008
[17] C. C. Cheng, T. S. Chang, K. B. Lee, “An In-Place Architecture for the Deblocking Filter in H.264/AVC,” IEEE Transactions on Circuits and Systems for Video Technology, 2006
[18] C. C. Cheng, T. S. Chang, “A Hardware Efficient Deblocking Filter for H.264/AVC,” IEEE Consumer Electronics, 2005
[19] T. M. Liu, W. P. Lee, C. Y. Lee, “An In/Post-Loop Deblocking Filter With Hybrid Filtering Schedule,” IEEE Transactions on Circuits and Systems for Video Technology, 2007
[20] C. M. Chen and C. H. Chen, “Configurable VLSI Architecture for Deblocking Filter in H.264/AVC,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2008
[21] The H.264/AVC Reference Software (JM18.0), http://iphome.hhi.de/suehring/tml/download/
校內:2021-12-31公開