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研究生： 何偉立
He, Wei-Li
論文名稱： 使用記憶體內運算架構實現一個極低功耗之語音活動檢測神經網路
A Computing-in-Memory Architecture for Ultra-Low Power Voice Activity Detection Neural Network
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2022
畢業學年度： 110
語文別： 英文
論文頁數： 126
中文關鍵詞： 機器學習 、記憶體內運算 、語音活動檢測 、混合精度神經網絡 、類比計算 、軟硬體共同設計
外文關鍵詞： machine learning, computing-in-memory, voice activity detection, hybrid precision neural network, analog computation, software and hardware co-design
相關次數： 點閱：119  下載：1 
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    • 本論文是第一個基於記憶體內運算實現專用於語音活動檢測神經網絡中分類器的設計。提出的靜態隨機存取記憶體完美地融入逐漸趨近式類比數位轉換器用來執行類比運算以降低能量消耗，且可避免資料誤寫。本設計從傳統的記憶體內運算電路中移除了數位至類比轉換器，以便後續將該分類器與前端類比特徵提取電路整合在一起，可以大大降低能量消耗和面積成本。透過軟硬體共同設計，提出了一個混合精確度的語音活動檢測神經網絡，且可以預測輸入範圍以防止逐漸趨近式類比數位轉換器量化時不必要的切換，並以超低的面積及能量消耗在極低信噪比的信號中執行語音活動檢測任務。本論文中一共設計並下線兩個晶片，分別是基於記憶體內運算之神經網路中的分類器電路和整合之完整語音活動檢測系統。
    第一個晶片——基於記憶體內運算實現之語音活動檢測神經網路中的分類器，採用台積電 180奈米 CMOS 標準 1P6M 製程實作晶片，其中晶片面積為 0.42 mm^2。在以 Dolphin Design 作為資料集且信噪比為3dB的輸入訊號情況下，此晶片的人聲抓取率(VDV) 及 噪音誤判率(NDV) 分別為 97% 和 5.2%，人聲抓取延遲為 30毫秒，能量消耗為 526奈瓦。
    第二個晶片——完整的語音活動檢測神經網絡，其為第一個晶片 (分類器) 與前端類比特徵提取電路整合而成的，同樣採用台積電180奈米CMOS標準1P6M製程製造，面積為1.1 mm^2。一樣在以 Dolphin Design 作為資料集且信噪比為3dB的輸入訊號情況下，此晶片的人聲抓取率(VDV) 及 噪音誤判率(NDV) 分別為 97% 和 3.4%，人聲抓取延遲為 32 毫秒，能量消耗為 2660 奈瓦。

    This thesis is the first design that proposes a computing-in-memory-based classifier dedicated to a voice activity detection neural network (VAD NN). The proposed 8T static random-access memory (SRAM) perfectly merges into SAR ADC and performs the analog computation to reduce the power consumption and even avoid read-disturbance. The digital-to-analog circuit (DAC) is removed from the convention CIM circuit to integrate this classifier with the front-end analog feature extractor circuit, which can greatly decrease the power and area consumption. Through software and hardware co-design, a hybrid precision voice activity detection neural network is proposed that can predict the input range to prevent SAR ADC unnecessary switching and execute classification tasks in extremely low SNR signals with ultra-low area and power consumption. We designed and tapped out two chips, including a computing-in-memory-based classifier circuit and a complete voice activity detection system.
    The first chip - a computing-in-memory-based classifier dedicated to a voice activity detection neural network - was fabricated in TSMC 180-nm CMOS standard 1P6M technology, and the CIM-based VAD NN occupies the area of 0.42 mm^2. The measurement result shows that VDV and NDV are 97% and 5.2%, respectively, and 30ms latency with 526nW power consumption on the Dolphin Design dataset with the 3dB SNR input signals.
    The second chip - a complete voice activity detection neural network - is developed after integrating with the front-end analog feature extractor, which was also fabricated in TSMC 180-nm CMOS standard 1P6M technology, whose area consumes 1.1 mm^2. The measurement result shows that VDV and NDV are 97% and 3.4%, respectively, and 32ms latency with 2660nW power consumption on the Dolphin Design dataset with the 3dB SNR input signals.

    摘　要 I Abstract III List of Tables IX List of Figures X Chapter 1　 Introduction 1 1.1　Background and Motivation 1 1.2　Thesis Organization 3 Chapter2　 Basics of Voice Activity Detection (VAD) Neural Network 4 2.1　Subfield in Artificial Intelligence 5 2.2　Neural Network Fundamentals 7 2.2.1　From Neural Networks to DNNs 7 2.2.2　Training Versus Inference 9 2.2.3　MLP and CNN 13 2.3　Compression of Neural Network 18 2.3.1　Pruning 18 2.3.2　Quantization 20 2.4　Voice Activity Detection Neural Network 23 2.5　Relative Works of Voice Activity Detector (VAD) 28 2.5.1　Analog Signal Processing VAD with NN-based Mixed-Signal Classifier 28 2.5.2　All-Analog Voice Activity Detector 32 2.5.3　Time-Domain CNN based VAD 34 2.5.4　Summary of VAD Relative Works 37 Chapter 3　 Basics of Computing-in-Memory 39 3.1　Memory Hierarchy 40 3.2　Von-Neumann Bottleneck 41 3.3　In/Near Memory Computation 43 3.4　Sub-circuits in Computing-in-Memory Architecture 45 3.4.1　Digital to Analog Converter 46 3.4.2　SRAM Cell 51 3.4.3　Analog to Digital Converter 54 3.5　Relative Works of Computing-in-Memory (CIM) 60 3.5.1　The First Prototype of Computation Within SRAM 60 3.5.2　A Convolutional Computation Within SRAM 64 3.5.3　A LCC-based 6T SRAM CIM Macro 66 3.5.4　Summary of CIM Relative Works 68 Chapter 4　 A Computing-in-Memory Architecture for Ultra-Low Power VAD Neural Network 70 4.1　Introduction 70 4.2　Proposed VAD Neural Network Architecture 72 4.2.1　Software Implementation of VAD Neural Network 72 4.2.2　Hardware Implementation of VAD Neural Network 76 4.3　Adopted Techniques of SAR ADC 85 4.3.1　The Monotonic Switching Method 85 4.3.2　Direct Switching Method and Compact Combinational Timing Control 87 4.4　Circuit Implementation 88 4.4.1　SRAM Array and Peripheral Circuits 88 4.4.2　Dynamic Comparator 90 4.4.3　Capacitive DAC 93 Chapter 5　 Simulation and Measurement Results 96 5.1　The First Chip – A Classifier in VAD System 97 5.1.1　Chip Layout and Floor Plan - CIM-based Classifier 97 5.1.2　Post-Layout Simulation Results - CIM-based Classifier 99 5.1.3　Die Micrograph and Measurement Setup - CIM-based Classifier 103 5.1.4　Measurement Results - CIM-based Classifier 106 5.2　The Second Chip – Complete VAD Neural Network 110 5.2.1　Chip Layout and Floor Plan - Complete VAD NN 110 5.2.2　Post-Layout Simulation Results - Complete VAD NN 111 5.2.3　Die Micrograph and Measurement Setup - Complete VAD NN 112 5.2.4　Measurement Results - Complete VAD NN 114 Chapter 6　 Conclusion and Future Work 119 Reference 122

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