由於現場可程式邏輯閘陣列(Field Programmable Gate Array, FPGA)具有靈活的可重構性、高性能和低開發週期等優點，許多基於FPGA的卷積神經網路(Convolutional Neural Network, CNN)加速器相繼被提出。儘管FPGA具有很多優點，但FPGA平台也有一些獨特的缺點，例如有限的硬體資源和晶片外記憶體頻寬。為了解決這個問題，先前大部分研究都採用設計空間探索(Design space exploration)技術來尋找在這些限制底下的最佳解。然而，他們僅探索數位訊號處理模組(Digital Signal Processing, DSP )的計算能力，忽略了可利用查找表(Lookup-table, LUT)來進行算術運算的選擇，而這可能會錯過一些設計空間。此外，在討論硬體限制時，現有文獻往往只討論DSP和區塊隨機存取記憶體(Block RAM, BRAM)，而忽略了LUT的重要性。
為了解決這個問題，本論文在設計空間探索中引入了基於 LUT 的計算單元。為了進一步提高 LUT 的使用效率，本論文使用捨棄式乘法器(Truncated Multiplier)來實現CNN的乘法運算，並提出一種改良的捨棄乘法補償方法和一種基於L1範數的核心選擇方法，以減少整體推理誤差。本論文採用目前常被使用的行固定資料流(row-stationary dataflow)為目標架構，相關設計空間探索是在基於FPGA特性的硬體限制下進行的，並基於探索結果，本論文在內含xc7z020 FPGA的Xilinx PYNQ-Z2開發版上實現VGG-16的卷積層加速器。實現結果顯示，於推理應用時，其平均性能在1.25億赫茲的操作頻率下可達到每秒570.20億個算術處理，相較於之前的研究成果，所產出之CNN加速器具有較佳的資源使用效率。

Many FPGA-based CNN accelerators have been proposed recently in the literature because FPGA design can provide several advantages over conventional ASIC design, such as flexibility and short development round time. However, there exist some design constraints for FPGA-based platform such as the limited hardware resource and off-chip memory bandwidth. To deal with the problem, most previous works adopted design space exploration to find the optimal solution. However, they only explore the computational capability of DSP modules and ignore the possibility of using lookup-tables (LUTs) to implement the arithmetic operations such that some design space may be missing. Moreover, when considering hardware constraints, only DSP and BRAM are discussed and the role of LUTs is ignored.
To address the above-mentioned problem, this thesis incorporates the LUT-based computing unit into the design space exploration. To further increase the efficiency of LUT usage, the multiplier is implemented with the truncated multiplier. An improved compensation method for truncated multiplier and a L1-norm-based kernel selection method are also proposed to reduce the overall inference error. The row-stationary dataflow is selected as our targeted architecture because of its high bandwidth efficiency. The design space exploration is executed under the hardware constraint and the characteristics of FPGA, and a CNN accelerator is implemented on the Xilinx PYNQ-Z2 with FPGA part xc7z020. The average performance can achieve up to 57.02 GOPS @ 125 MHz for the convolutional layers in VGG-16. Experimental results reveal that the resource efficiency of our implementation is better than that of the previous works.

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