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研究生： 林璟汶
Lin, Jing-Wun
論文名稱： 符合電子系統層級設計概念之可參數化超純量亂序執行微處理器設計、分析與實現
Design, analysis, and implementation of a parameter-based out-of-order superscalar microprocessor conforming to ESL methodology
指導教授： 陳中和
Chen, Chung-Ho
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 中文
論文頁數： 60
中文關鍵詞： 微處理器 、超純量架構 、管線架構
外文關鍵詞： Microprocessor, Pipeline, Reservation Station, Superscalar, Register Update Unit
相關次數： 點閱：80  下載：3 
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    • 本論文探討如何將目前晶片系統最常使用的ARM處理器，設計成超純量亂序執行之高性能微處理器。將管線化設計的ARM處理器超純量化是非常複雜，需要詳細分析其適用的超純量架構包括:Reservation Station Base與Register Update Unit Base，還要解決ARM特有的多重執行模式和暫存器檔案、定址模式、複雜指令與條件執行指令等。我們將分為架構層面與指令層面兩方面探討、分析並加以解決。
    我們採用Register Update Unit Base設計一個九級管線的超純量架構，而ARM特有問題當中最為重要的就是複雜指令與條件執行指令的處理。複雜指令的拆解不但在拆解過程中需要注意，在執行與中斷處理上也必須特別處理。對於條件執行指令的處理不但關係動作的正確性，對於效能也具有極大的影響。我們對於效能的增進使用了四種方式，其中最具效果的就是條件執行指令處理的改進技術。根據各級設計與調整的結果，我們得到高於五級管線處理器30%以上的效能結果。

    In this thesis, we design an out-of-order superscalar microprocessor which is based on the popular ARM microprocessor. Many micro-architecture complexities arise when transforming an ARM-based pipelined processor into a superscalar one. The first is to choose a superscalar architecture from a reservation station based model or a register update unit based processor model. And the second one is to deal with the special characteristics of the ARM architecture which has multiple execution modes, multi-banked register files, addressing modes, CICS-like instructions, and conditional executing instructions.
    Based on the simulation results, we use the register update unit architecture to design a nine-stage pipelined superscalar processor. We develop techniques to handle the CICS-like instructions and conditional executing instructions for the ARM ISA, and find that the operations of conditional executing instructions are the key factor that affects the performance. The proposed superscalar processor has achieved 30% higher performance than that of the traditional five-stage pipeline processor.

    摘要 I Abstract II 誌謝 III 目錄 IV 表目錄 VII 圖目錄 VIII 第1章 序論 1 1.1 研究動機 1 1.2 研究貢獻 1 1.3 論文編排 2 第2章 背景知識 3 2.1 亂序執行之超純量架構 3 2.1.1 Types of issue window 3 2.1.2 Types of register rename scheme 5 2.2 超純量微處理器 5 2.2.1 DEC Alpha 21264 5 2.2.2 HP PA-8000 6 2.2.3 IBM PowerPC 604 6 2.2.4 IBM PowerPC 620 6 2.2.5 MIPS R10000 7 2.2.6 Intel P6 architecture 7 2.2.7 Intel NetBurst architecture 7 2.2.8 StrongARM 8 2.2.9 ARM Cortex-A8 8 2.2.10 結語 8 2.3 ESL design concept 8 2.4 ARM v4指令集 9 2.4.1 指令集特性 9 2.4.2 指令類型 10 2.4.3 執行模式 10 2.4.4 暫存器檔案 11 2.4.5 中斷處理 12 第3章 架構設計與分析 14 3.1 超純量架構與管線架構之差異 14 3.1.1 架構層面 14 3.1.2 指令層面 15 3.2 亂序執行之超純量架構選擇 16 3.2.1 Reservation station model 16 3.2.2 Register update unit model 17 3.2.3 ARM架構適用模型 18 3.3 Register rename scheme 20 3.4 Conditional execution problem 22 3.5 結語 25 第4章 架構實現 26 4.1 Overview 26 4.1 Instruction fetch stage 27 4.2 Instruction decode stage 29 4.3 Branch predictor 30 4.4 Register rename stage 32 4.5 Issue window 35 4.5.1 Buffer instructions 35 4.5.2 Wake-up instructions 37 4.5.3 Select instructions 37 4.5.4 External instructions 38 4.5.5 Commit instructions 38 4.6 Register file stage 39 4.7 Function unit stage 39 4.8 Wake-up stage 40 4.9 Instruction commit stage 41 4.10 Exception handler 42 4.11 結語 43 第5章 實驗環境與數據分析 44 5.1 環境架設 44 5.2 測式程式與軟體平台 45 5.3 實驗數據與結果分析 47 5.3.1 Basic form 48 5.3.2 Branch prediction 48 5.3.3 External unit enhancement method 50 5.3.4 Conditional execution management method 51 5.3.5 Other arguments 51 5.3.6 Execution parallelism 53 5.4 結語 54 第6章 結論與未來展望 55 6.1 結論 55 6.2 未來展望 56 參考文獻 57 自述 60

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