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研究生： 張凱行
Chang, Kai-Hsing
論文名稱： 一個基於子空間追蹤演算法之語音強健系統及其硬體設計
Algorithm/Hardware Design of a Subspace Tracking Based Speech Enhancement System
指導教授： 王駿發
Wang, Jhing-Fa
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 英文
論文頁數： 72
中文關鍵詞： 子空間追蹤 、雜訊消除 、硬體設計
外文關鍵詞： hardware design, subspace tracking, noise reduction
相關次數： 點閱：93  下載：4 
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    • 　　在此篇論文中，我們基於子空間追蹤演算法設計一個語音強鍵系統。所提出的演算法中，整合了聽覺分頻濾波推架構來做為前處理。藉由實驗模擬結果發現，以TAICAR資料庫音檔來做測試，所提出的架構比傳統子空間方法語音強健效果較好。由其在汽車雜訊環境中，低頻雜訊 (低於1KHz) 經過分頻濾波推後能被有效的去除。對於即時系統應用，我們設計一個子空間追蹤演算法的管線化超大型積體電路架構。不用延持技術，應用前瞻技術方法推導硬體，子空間追蹤演算法中的資料相依的危障能被順利解決。我們所推導的管線子空間演算法架構之收斂速度比延持的PASTd架構還要更快。在硬體設計中，為了減少晶片面積，我們共用乘法器來分擔多個乘法，這使得乘法器數目減少相對節省面積大小，也使得且濾波器階數和乘法器數目無關。我們所推導出來的子空間追蹤演算法實現於ARM-Based Aletra EpxA10發展板上。其工作頻率為9.7MHz。

    　　In this thesis, we describe a design of signal subspace speech enhancement based on subspace tracking algorithm. The proposed algorithm incorporates a perceptual filterbank which is derived from psycho-acoustic model with signal subspace processing. The experimental results which were obtained by testing TAICAR database show that our approach is better than conventional subspace methods. The low frequency noises (below 1KHz) in car noisy environments are suppressed efficiently after applying the perceptual filterbank. For real time applications, we derive a pipelined VLSI architecture of the subspace tracking algorithm. The data hazard of subspace tracking algorithm is solved by using Look-Ahead method without delayed updating. The convergence rate of our architecture is faster than those of delayed PASTd architectures. To save the chip area, a shared technique for the arithmetic of multiplication units is adopted. It makes the number of multipliers be independent with the filter length. This architecture has been realized in ARM-based ALTERA EPXA10 Development Board with frequency at 9.7MHz. Simulation results are presented to validate our algorithm and hardware architectures.

    中文摘要 iv Abstract v Acknowledgment vi Lists of Figures x Lists of Tables xii Chapter 1 INTRODUCTION 1 1.1 Speech Enhancement Algorithms and Applications 2 1.2 Signal Subspace Technique and Applications 3 1.3 Related Studies 4 1.4 Motivation 7 1.5 Organization of Thesis 9 Chapter 2 SINGAL SUBSPACE BAESD SPEECH ENHANCEMTN 10 2.1 Problem Description 10 2.2 The Decomposition of Signal and Noise Subspace 10 2.2.1 Concept of Signal and Noise Subspace 11 2.2.2 Subspace Decomposition Using Karhunen-Lo`eve Transformation 12 2.3 Subspace Estimation from Noisy Data 14 2.4 Rank Estimation 14 2.5 Linear Signal Estimators 15 2.5.1 Linear Least Square Estimator 16 2.5.2 Minimum Variance Estimator 16 2.5.3 Time Domain Constraint 17 Chapter 3 THE PROPOSED SPEECH ENHANCEMENT ALGORITHM 19 3.1 Overall Speech Enhancement System 19 3.2 Perceptual Filterbank 20 3.3 Subspace Tracking Algorithm 25 3.3.1 Comparison of subspace tracking algorithms 26 3.3.2 Projection Approximation Subspace Tracking (PAST) Algorithm 27 3.3.3 Projection Approximation Subspace Tracking Deflation (PASTd) Algorithm 28 Chapter 4 HARDWARE DESIGN OF SUBSPACE TRACKING ALGORITHM 30 4.1 Design Issues of The PASTd Algorithm 30 4.2 The Proposed Pipelined PASTd Architecture 31 4.2.1 Look-Ahead Substitution for PASTd Architecture 31 4.2.2 Sharing Multiplication Arithmetic Units Description 33 4.2.3 The Proposed Architecture 35 4.2.4 Converge Characteristic of the Proposed PASTd Architecture 39 4.2.5 Apply Pipelined PASTd Architecture to Proposed Speech Enhancement System 41 4.3 The Hardware Design Evaluation 41 4.3.1 Real-Time Issues 42 4.3.2 Precision Analysis 42 Chapter 5 EXPERIMENTAL RESULTS AND HARDWARE VERILFICATION 45 5.1 The Evaluation of Proposed Speech Enhancement Algorithm 45 5.1.1 TAI-CAR Data Base Description 46 5.1.2 Performance of the Method for Additive Car Noise 47 5.1.3 Performance of the Method for Real Environment In-Car Noise 52 5.2 SOPC Implementation of the Proposed Pipelined Architecture Algorithm 54 5.2.1 Introduction to SOPC 56 5.2.2 Design Flow and Strategy 56 5.3 Hardware Functional Simulation Results 59 5.4 Chip Features 61 Chapter 6 CONCLUSIONS AND FUTRURE WORKS 65 REFERENCES 67

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