系統單晶片(SoC)包含越來越多的模塊，使得電源網路規劃問題(Powerplanning)變得越來越複雜。如何使用最少的繞線資源滿足需求，是非常困難的問題。為了避免發生電壓下降(IR-drop)及電遷移效應(Electromigration)，傳統電源網路規劃常使用過多的電源網路線，而浪費不必要的繞線資源，增加晶片成本。往往在繞線完成後，才發現在晶片某些位置出現繞線擁擠，因此，勢必要去更新模塊擺置的位置，或是移除某些電源網路線來解決，否則會導致上市時間(time-to-market)延長。為了節省繞線資源並提高整體電源網路之可繞度(Routability)，應用機器學習(Machine learning)的技術，其可達到溯往既來，能根據前人的經驗，預測未來會發生的結果;因IC Compiler需耗費大量時間估計全域繞線擁擠度，故透過機器學習能更快速獲得結果。機器學習的模型訓練上應用數十個特徵以學習ICC擁擠圖所呈現全域繞線之擁擠區域。根據機器學習預測出擁擠圖結果便能避免電源線段擺置於過度擁擠區域，再搭配提出的列式(Row-style)電源網格促進預先擺置模塊的連接，進一步獲得較佳的可繞度。另外，使用有效電源線段寬度，不僅減少繞線資源的浪費外還發揮更高效能的供電。此為第一篇提出透過機器學習預測擁擠度並使用線性規劃演算法最小化電源網路繞線面積並同時考量可繞度的論文。實驗結果表明，列式電源規劃顯著提高具有多個模塊電路之可繞度，再透過機器學習所預測擁擠圖優化整體電源網路，便能更進一步提升可繞度。

SoC contains more and more macros, which makes the powerplanning problem more and more complicated. It is a very difficult problem that use the minimum routing resources to achieve the target. In order to avoid IR-drop and electromigration effect, traditional powerplanning often uses too many power stripes lead to waste unnecessary routing resources and increasing costs. Only after the routing complete can find that congestion in some locations on the chip. Therefore, it is imperative to update the position of the macro placement, or remove some power stripes to solve these problems. Otherwise, it will lead to time-to-market extension. In order to save routing resources and improve the routability of the overall power network, machine learning technology is applied. It can be traced back to the past and prediction of the result based on previous experience. Because IC Compiler needs to spend a lot of time estimating the degree of global routing congestion, it is faster to obtain results through machine learning. Dozens of features are applied to machine learning model training to learn about the congestion regions of the global route presented by the IC Compiler congestion map. According to machine learning prediction of the result, the high congestion region can be avoided to place the power stripe. Then with the proposed row-style power grid to facilitate the connection of the pre-placed macros, and further to obtain better routability. In addition, the use of an effective power stripe width (ESW) not only reduces the waste of the routing resources but also enables a higher-efficiency voltage supply. This is the first paper that proposes predicting congestion by machine learning and using a linear programming algorithm to minimize the power network routing area while taking into account the routability. The experimental results show that row-style powerplanning can significantly improve the routability of circuits with multiple macros, and then optimize the overall power network through machine learning predicted congestion maps, which can further improve the routability.

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