低電容突波抑制保護元件，主要是應用在高速傳輸I/O Ports、USB2.0/3.0、HDMI、IEEE1394、DVI等電子產品，防護瞬間過度電壓應力與靜電放電(ESD)對積體電路與電子元件或系統的破壞。針對先進VLSI與電子產品電路的保護，其主要趨勢在尋求低電壓與低電容的防護元件，達成有效的保護元件及符合資料高速傳輸的需求。本論文提出高分子導電分子材料搭配絕緣粉末，調配混合成適用於低電容突波抑制器之PASTE，而元件設計概念是以被動元件製程領域作基礎理論去設計此防護元件，主體利用現有陶瓷基板為元件本體結構設計，在經由網版設計在本體結構上方印刷一層不同的間隙導體，再以習知印刷製程技術方式，將低電容突波抑制器之PASTE覆蓋在兩導體的間隙內，並經由電阻製程習知塑燒技術，將元件燒結適當溫度製成靜電防護元件；而此防護元件在經外加靜電放電轟擊測試後，量測靜電放電轟擊後的電容、Trigger voltage及漏電流相關數據，並藉由量測結果來討論此不同的佈局樣式，在相同工作區面積、不同間隙、固含量與溫度比下，對於元件效能是否達到靜電防護元件低電容與低崩潰電壓的需求，並藉此晶片型防護元件可設計整合於先進積體電路或應用於獨立系統的靜電防護元件中。根據研究試驗結果，本論文研究製作之低電容突波抑制元件，的確可以符合低電容低電壓突波抑制元件的特性需求與應用。同時在此研究中，我們藉由DSC熱分析量測系統比對測試後的元件Trigger voltage與溫度及間隙變化，可以清楚的了解元件相互參數調整知搭配性，可幫助靜電放電轟擊測試機制的分析及進行元件結構之最佳化設計。

Ultra-Capacitance Surge suppression protection component, primarily used in high-speed I / O ports, USB2.0/3.0, HDMI, IEEE1394, DVI and other electronic products protection, and transient over-voltage stress and electrostatic discharge (ESD) of Integrated Circuits and electronic components or system damage. For advanced VLSI and electronic circuit protection products, the main trends in the search for low-voltage and low capacitance protection components, to achieve effective protection of components and with the high-speed data transmission needs. This paper presents conductive polymer molecular materials with insulating powder, mixed into the deployment of surge suppressors for low capacitance of paste, while the component design concept is based on the field of passive components, manufacturing process to make the basic theory to design the protective components, the main use of the existing ceramic substrate for the component body structure design, screen design in the body through the structure of the gap at the top of the printing layer of a different conductors, and then to learning to know the printing process technologies approach the low capacitance of the surge suppressor paste cover the gap in the two conductors, and by the resistance of plastic burning process technology, the temperature of sintering parts made of electrostatic protection element, and this protection through the external ESD components in bombardment tests, measurement of capacitance electrostatic discharge after bombardment, Trigger voltage and leakage current data, and the volume measured by the results of future discussion of the layout of this different style of work in the same area, different clearance, solid content and temperature than the next, for the attainment of performance components, a low capacitance ESD protection devices with low breakdown voltage requirements and to chip-based protection devices can be designed to integrate with the advanced Integrated Circuits or used independent of the electrostatic protection element in the system. Based on the test results, this thesis production of low capacitance, surge suppression components can indeed consistent with low-capacitance low-voltage surge suppression characteristics of the demand components and applications. At the same time in this study, we measured by DSC thermal analysis system for testing of components than the Trigger voltage and temperature and the gap changes, The best design can clearly understand each element together with knowledge of parameter adjustment can help ESD bombardment test mechanism analysis and carry out structural components.

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