本論文針對ANSI S1.11 所規範的Class2及Class1兩種等級的濾波器組，提出了一個新穎的演算法與其硬體架構設計的實現方法。在濾波器組的設計流程中，主要可分成五個部分：(1)為找尋適當全通濾波器係數a值的演算流程；(2)設計一組低通濾波器使其符合ANSI規格；(3)找尋最少點數M值的離散餘弦轉換；(4)設計低通濾波器D及I ；(5)加入餘弦轉換優化及延遲補償機制，降低整體運算量及改善群延遲的現象，使得分頻的語音信號在最後合成時能夠有效的提升每個頻帶的整體延遲差異，提升了語音品質與識別度。
在實作應用方面，分別採用了2種實作數位助聽器方式：(1) FPGA開發版軟硬體整合實作；(2) 晶片下線實作。最後希望聽障患者可以使用本設計，來做調整每個頻帶的增益並使聽覺達到和正常人聽覺一致。
相較於2013年由劉志尉教授等人所提出的濾波器組設計方案，本論文提出的設計藉由調整每個頻帶的整體延遲差異時間，有效的改善哈斯效應，同時也減少了25%乘法運算量，在未來助聽輔具的應用與整合上應可提供更多的選擇性。

In this thesis, we propose a novel algorithm whose hardware architecture design is based on the specification of ANSI S1.11 Class1 and Class2 filter banks. The filter bank design can be divided into four primary parts: the first one is to find a suitable all-pass filter coefficient; the second one is to design a set of low-pass filter conformed with ANSI specification; the third one is to find the minimum transform length of discrete cosine transform (DCT); the fourth one is to design two sets of low-pass filter D and filter I; Finally, in order to reduce computational complexity and Hass effect, werespectively propose the optimized DCT computation and compensative mechanism. it makes the speech signal have the same and correct time slot in every band. The quality and recognition of voice is enhanced by the proposed compensation mechanism.
In implementation, we used the following two ways: (1) Integrate with software and hardware by FPGA; (2) Chip implementation. We hope that people with hearing disabilities can adjust the gain of each band to achieve normal hearing level by this design.
Compared to Liu et al.’s filter bank design in 2013, we not only improved Hass effect by adjusting the difference of group delay of each band, but also reduced 25% of multiplications. Developing hearing aids is worthwhile in the future. This thesis provides more choices for designing and integrating hearing aids.

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