摘要
MP3 音樂壓縮格式為MPEG 所制定的數位音響壓縮標準，其優越性已被廣泛地應用於網路傳輸及無線多媒體系統之播放與儲存。其中以逆改良型離散餘弦轉換(IMDCT)與合成濾波器組(Synthesis Filter Bank)是MP3 解碼流程中時間複雜度高且計算方式固定的兩個步驟。
在本論文中，我們將逆改良型離散餘弦轉換和合成濾波器組中的矩陣化轉換(Matrixing)皆設計成遞迴式硬體架，並以軟/硬體共同設計的方式將MP3 播放系統驗証於SoC 發展平台上。除此之外，硬體與發展平台之間的設計方式是採用可擴充式架構，可以任意增添或更改系統模式。
遞迴式逆改良型離散餘弦轉換與矩陣化轉換的硬體設計是使用Verilog HDL 撰寫，採用Xilinx Foundation 4 軟體模擬與合成，燒錄於發展平台上的FPGA，最後再搭配ARM 處理器以達成MP3 播放系統。其硬體架構的合成結果為103k 邏輯閘，時脈速度為14.3MHz。

MP3, the well-known abbreviation of MPEG-1 audio Layer 3 is categorized one of the MPEG (Moving Picture Experts Group) standards for digital audio compression. For its versatile superiority, MP3 has been widely used in Internet transmission and wireless multimedia communication or storage applications. The inverse modified discrete cosine transform (IMDCT) and synthesis filter bank are the two critical procedures with high time complexity but regular computation. In this thesis, we propose the recursive hardware structures for IMDCT and matrixing transform of synthesis filter bank. Furthermore, MP3 player system following Hardware/Software co-design methodology is developed and verified on SoC development platform. Besides, the design of interface between hardware and development platform is expandable. System mode can be added or changed.
The hardware design of recursive inverse modified discrete cosine transform and matrixing is coded by Verilog HDL and then simulated and synthesized with Xilinx Foundation 4. The synthesized circuit is downloaded into FPGA on the development platform and cooperates with ARM processor to complete the MP3 system. The synthesis results show that gate count is 103k gates and clock rate is 14.3 MHz.

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