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研究生： 張力仁
Chang, Li-Jen
論文名稱： 一個不需校正之十二位元每秒取樣一千萬次逐漸趨近式類比數位轉換器
A 12-bit 10-MS/s Calibration-Free Successive-Approximation Analog-to-Digital Converter
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 115
中文關鍵詞： 逐漸趨近式類比數位轉換器 、不需校正 、超取樣 、殘值超取樣 、偵測與順延演算法
外文關鍵詞： Successive approximation register (SAR) analog-to-digital converter (ADC), Calibration-free, Oversampling, Residue Oversampling, Detect-and-skip (DAS) algorithm
相關次數： 點閱：146  下載：31 
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    • 本論文呈現一個使用180奈米製程所研製的不需校正之十二位元每秒取樣一千萬次逐漸趨近式類比數位轉換器。
    本次實作採用了殘值超取樣和偵測與順延演算法兩種技術。殘值超取樣技術會對於每一個取樣的電壓，藉由調整電容陣列中的電容、將之對應於不同的權重來產生多組的殘餘電壓，並透過量化多組的殘餘電壓以產生高精確度的數位碼。除此之外，解析數位碼的切換過程可以透過切換與順延演算法進行優化，使得由大電容不匹配所產生的不匹配誤差變小。透過這兩種技術的結合，在沒有複雜校正方法下，可以有效降低由雜訊和電容不匹配所造成的影響。
    本論文所研製的十二位元逐漸趨近式類比數位轉換器的面積約為0.47mm2，此類比數位轉換器在1.95伏特以及1.9伏特的電壓供應下可以操作在一千萬赫茲(10-MS/s)及六百萬赫茲(6-MS/s)的取樣頻率。實測效能顯示，此雛型晶片在一千萬赫茲的取樣頻率以及奈奎斯特輸入頻率下，可以達到有效位元為10.32位元 (SNDR為63.87 dB)、在600萬赫茲的取樣頻率(6-MS/s)和200萬赫茲(2MHz)輸入頻率下，有效位元為10.97位元(SNDR為67.79 dB)，得到的轉換效率分別為185.3fJ/conversion-step和128fJ/conversion-step。

    A 12-bit 10-MS/s calibration-free successive-approximation register (SAR) analog-to-digital converter (ADC) in 180-nm process is presented in this thesis.
    This work adopts two techniques, namely residue oversampling and detect-and-skip (DAS) algorithm. For each sample voltage, the residue oversampling technique generates different residual voltages by dynamically rearranging different weights to different capacitors in the capacitor array. These residual voltages would be quantized to generate digital codes with higher accuracy. Besides, the switching procedure could be optimized by the detect-and-skip (DAS) algorithm, which could effectively reduce the mismatch error caused by the MSB capacitors, during conversion. By combining the two techniques, the impacts caused by noise and capacitors’ mismatches could be improved significantly without any complex calibration scheme.
    The proof-of-concept 12-bit SAR ADC occupies 0.47mm2. It operates at 10-MS/s and 6-MS/s with 1.95-V and 1.9-V supplied voltages, respectively. The measurement results show that the prototype ADC achieves 63.87 dB SNDR at 10-MS/s with a Nyquist-rate input and 67.79 dB SNDR at 6-MS/s with a 2MHz input. The figure-of-Merit (FoM) is 185.3fJ/conversion-step and 128fJ/conversion-step, respectively.

    摘　要 III Abstract V List of Tables XI List of Figures XII List of Abbreviations XVI Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Organization of the Thesis 4 Chapter 2 Fundamentals of Analog-to-Digital Converters 5 2.1 The Basics of Analog to Digital Converter 5 2.1.1 Quantization Error 6 2.1.2 Resolution 8 2.1.3 Accuracy 9 2.2 Static Specification 10 2.2.1 Offset Error 10 2.2.2 Gain Error 11 2.2.3 Nonlinearity 13 2.3 Dynamic Specification 17 2.3.1 Signal-to-Noise Ratio (SNR) 17 2.3.2 Signal-to-Noise and Distortion Ratio (SNDR) 19 2.3.3 Effective Number of Bits (ENOB) 19 2.3.4 Spurious-Free Dynamic Range (SFDR) 20 2.3.5 Total Harmonic Distortion (THD) 21 2.3.6 Effective Resolution Bandwidth (ERBW) 22 2.3.7 Figure of Merit (FoM) 23 Chapter 3 Design Techniques for High-Resolution SAR ADCs 24 3.1 Successive-Approximation Register (SAR) ADC 24 3.1.1 The Concepts of SAR ADC Operation 25 3.1.2 Circuit Operation of the SAR ADC Architecture 28 3.1.3 Performance Limitations of High-Resolution SAR ADCs 31 3.2 Oversampling 36 3.3 Techniques for Nyquist-Rate ADCs 41 3.3.1 Pipeline SAR Design 41 3.3.2 Majority-Voting Technique 45 3.3.3 Adaptive-Averaging Technique 46 Chapter 4 A 12-bit 10-MS/s SAR ADC 49 4.1 Adopted Techniques 50 4.1.1 Residue Oversampling 50 4.1.2 Detect-and-Skip Algorithm 57 4.2 Architecture of the SAR ADC 60 4.2.1 Simplified-DEM Structure 60 4.2.2 Error-Tolerance Range 62 4.2.3 Architecture 64 4.2.4 Capacitor Switching Methods 67 4.3 Behavior-model Simulations 72 4.3.1 Behavior-model Simulations with Noise 73 4.3.2 Behavior-model Simulations with Capacitors’ Mismatches 74 4.4 Circuit Implementation 77 4.4.1 Bootstrapped Switch 77 4.4.2 Dynamic Two-Stage Comparator 80 4.4.3 DAS-Algorithm Implementation 83 4.4.4 Digital Error Correction Decoder 85 4.4.5 Capacitive DAC 87 Chapter 5 Simulation and Measurement Results 89 5.1 Layout and Chip Floor Plan 90 5.2 Simulation Results 93 5.3 PCB Design Consideration 97 5.4 Micrograph and Measurement Setup 98 5.5 Measurement Results 100 Chapter 6 Conclusions and Future Works 109 Bibliography 111

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