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研究生： 歐承政
Ou, Cheng-Jeng
論文名稱： 應用螞蟻演算法於多模式系統之兼顧效能與節能的匯流排通訊架構探勘
Bus-based Communication Architecture Exploration for Speed-sensitive Energy-efficient Multi-mode Systems using Ant Colony Algorithms
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 74
中文關鍵詞： 匯流排 、矩陣 、分享 、螞蟻 、通訊 、架構
外文關鍵詞： bus, matrix, shared, AXI, Ant, communication, architecture
相關次數： 點閱：99  下載：1 
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    • 由於製程的微縮，越來越多的應用可以被整合在單一晶片中，來因應多元化的使用需求，如H.264、MPEG等多媒體壓縮技術。在以匯流排通訊架構為主的設計下，矽智財(IP)間的傳輸與溝通也越來越複雜,因此在不同的傳輸架構上對於功率及整體效能上的影響也將會十分可觀。我們運用螞蟻演算法提出了一個可以同時考慮多種操作模式的快速通訊匯流排架構探勘方法，所提出的方法不但可以兼顧各個模式的執行效能，也能針對功率消耗做最佳化。
    我們所提出的探勘方法著重在可以同時考慮匯流排矩陣(Bus Matrix) 與分享匯流排(Shared-link) 的混和架構，此架構能在符合頻寬需求下保持適當的硬體成本及功率消耗。 在實驗結果中，提出的演算法展現了高度的尋解效率與準確性。不但如此，藉由不同效能限制下描繪出來的最佳功率曲線圖，可以看出通訊架構從分享匯流排架構演進到匯流排矩陣的過程。這可以幫助設計者了解在不同的效能需求下，所需要的硬體。

    As technology shrinking, more and more applications such as H.264, MPEG4 etc. could be integrated into a single chip for versatile demands. In bus-based design, the communication architecture plays an important role in system performance and power due to increasingly complexity of communication among Intellectual Properties (IPs). We proposed an efficient bus-based communication architecture exploration methodology for multi-mode systems using ant colony algorithm. The proposed method can explore communication architecture that not only meet performance constraints for all operating modes but also optimize the power consumption of the system on communication.
    The proposed exploration method focusing on hybrid communication architecture, capable of mixing a bus matrix and shared buses, that may achieve high utilization on bandwidth with feasible hardware cost and low power consumption. In the experimental results, the proposed methodology demonstrates its effectiveness in searching efficiency and accuracy. Furthermore, power/performance trade-off thus obtained can reveal the needs of transforming from shared bus to bus matrix and help designers to realize hardware under different constraints.

    Chapter 1 Introduction 1 1.1 Motivation 1 1.1.1 Multi-mode and multi-standard for multimedia application 1 1.1.2 Multimedia systems requirements 2 1.1.3 Impact of on-chip communication architecture 3 1.1.4 ESL design concept 5 1.2 Mode Balanced Communication Architecture and Trade off 6 1.3 Thesis Contributions 6 1.4 Thesis Organization 7 Chapter 2 Background 8 2.1 Ant Colony Optimization 8 2.2 Advanced eXtensible Interconnect(AXI) Protocol 11 2.2.1 Features of AXI 11 2.2.2 Architecture 11 2.2.3 Interconnect 13 2.2.4 Transaction ordering 14 2.3 Nonfunctional Performance and Power Estimation 15 Chapter 3 Related Work 17 3.1 AHB Based Communication Architecture Exploration and Synthesis Approaches 17 3.1.1 On-chip communication architecture optimization 17 3.1.2 Based on simulated annealing algorithm 20 3.1.3 Based on multi-objective genetic algorithm for multi-mode systems 22 3.2 AXI Based Communication Architecture Exploration and Synthesis Approaches 23 3.2.1 Low-power bus architecture composition 23 3.2.2 Bus matrix communication architecture synthesis for MPSOC 25 3.3 Summary 26 Chapter 4 AXI Estimator 28 4.1 Transaction Reordering in Bus Matrix and Shared-linked AXI 28 4.2 AXI Parameters 31 4.3 Proposed AXI Estimation Scheme 33 4.3.1 AXI performance modeling 33 4.3.2 AXI power modeling 36 4.3.3 System power/performance of AXI communication architecture 37 4.4 Verification Using CoWare 40 4.4.1 Example system description 40 4.4.2 Result of verification 42 4.5 Impacts of Bus Topology and Bus Arbitration 44 4.6 Summary 45 Chapter 5 Proposed Bus-based Communication Architecture Exploration for Multi-mode Systems 46 5.1 Problem Definition 46 5.2 Ant Path and Architecture Mapping 48 5.3 Proposed Algorithm 49 5.3.1 Parameter setup 50 5.3.2 The construction of ant solutions 51 5.3.3 Power and performance estimation 52 5.3.4 Branch and bound rule 52 5.3.5 Pheromone update 53 5.3.6 Ant local search 54 5.3.7 Stop criteria 54 Chapter 6 Experimental Results 55 6.1 Case 1：Effectiveness of Proposed Algorithm 55 6.1.1 Case description 55 6.1.2 Results and discussions 57 6.2 Case 2：Multiple Performance Constraints 60 6.2.1 Case description 60 6.2.2 Results and discussions 61 6.3 Case 3：Multi-Mode System – H.264 Encoder and Decoder 64 6.3.1 Case description 64 6.3.2 Results and discussions 67 Chapter 7 Conclusions and Future Works 69 7.1 Conclusions 69 7.2 Future Works 69 Reference 71

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