隨著製程技術的發展，使用矽做為主要半導體材料的金氧半場效電晶體不斷 地成功微縮，但是如果繼續發展下去很快的會碰到了物理極限的限制而導致無法 繼續提升性能。許多方式被提出來解決這個問題，鍺由於其較高的載子遷移率以及與矽製程較大的相容性，被視為是下個世代中有機會取代矽做為通道的半導體 材料。但是N型鍺與金屬接面會有較大的蕭基位位障而導致較大的接觸阻抗，所以如果我們要使用鍺做為金氧半場效電晶體的材料，降低N型鍺與金屬接觸阻抗是必要的。本論文探討利用插入介電層並搭配退火方式來降低N型鍺與金屬的接觸電阻及蕭特基位障，實驗流程包含離子佈值、ALD介電層沉積、E-beam金屬層沉積、RTA及MWA退火，此實驗流程更能確實模擬MOSFET中source/drain真實情況。
第一部分，以150oC摻雜磷離子進入鍺，接著使用低能量微波退火與傳統快速熱退火，並以TEM、四點探針量測並分析，發現使用快速熱退火溫度450oC持續時間10秒，低能量微波退火能量1200W持續時間75秒，皆能夠有效地將摻雜磷離子活化(activation)，使被磷離子破壞的非晶鍺完整修復為結晶鍺，其片電阻值分別低於63 ohm/sq及62 ohm/sq，故選定RTA 450 oC及MWA 1200W作為退火條件。
第二部分，利用介電層插入製程使用三氧化二鋁以及二氧化鈦做為介電層，藉由介電層厚度的改變，觀察蕭特基位障及接觸電阻之變化，並以J-V、I-T、TLM電性量測加以分析，發現三氧化二鋁及二氧化鈦厚度分別在2奈米及6奈米得到最低蕭特基位障及接觸電阻。進而發現二氧化鈦降低蕭特基位障及接觸電阻能力優於三氧化二鋁，由於二氧化鈦與鍺有較低的導帶差，因而在降低蕭特基位障之外還能達到較小的穿隧阻抗，以致於有較大的導通電流。並觀察到插入不同厚度的二氧化鈦之元件上發現隨厚度增加蕭基位位障反而降低，所以推斷介電層插入元件是以改變鎖定位置為主的方式調變蕭特基位障。
第三部分，探討利用不同退火方式下，對於分別插入2奈米三氧化二鋁及6奈米二氧化鈦元件之影響，實驗結果顯示經由傳統快速熱退火之三氧化二鋁及二氧化鈦蕭特基位障分別為0.4eV及0.18eV，微波退火方面蕭特基位障為0.35eV及0.14eV，而在接觸電阻方面各別降低十倍，發現使用微波退火更能獲得較低的蕭特基位障及接觸電阻，利用C-V、G-V計算出表面能態密度，實驗結果顯示由傳統快速熱退火之三氧化二鋁及二氧化鈦表面能態密度分別為3.31x1013 cm-2 eV-1及2.48x1013 cm-2 eV-1，微波退火方面表面能態密度降為7.45x1012 cm-2 eV-1及4.88x1012 cm-2 eV-1，由於微波退火加熱方式有別於傳統快速熱退火，微波退火主要特點是它的似光性、穿透性和非電離性，在似光性部分，微波與頻率較低的無線電波相比，更能夠像光線一樣地傳播和集中，不會因為較遠距離而變得更微弱；在穿透性方面，微波與紅外線相比，當微波照射在介質時更容易深入物質内部，才能有較高的穿越性；非電離性部分，微波的量子能量與物質相互作用時，不會改變物質分子的内部結構(只會去改變其轉動狀態)。
本論文提出插入介電層以降低蕭特基位障的物理機制，並解釋了厚度與效應，並比較出不同退火方式下，對於蕭特基位障及接觸電阻之改變，得到最佳退火方式、退火能量、介電層種類及厚度，對於提升N型鍺的金氧半場效電晶體，極具應用潛力。

With the rapid progress of nano-fabrication technology, Si based MOSFETs have been successfully scaled down to 20 nm regime. However, the continued scaling will be a problem due to several physical and technical limitations, and the device performance may not be improved by further scaling down. Many methods have been purposed to solve this problem, because of the higher carrier motilities and better process compatibility, Ge is considered as a potential candidate to replace silicon as the next generation channel material. However, the contact resistance between metal and n-type Ge is very high due to the high Schottky barrier height. In order to implement high performance Ge NMOSFETs, reducing the contact resistance of metal/n-type Ge is critical. This thesis explores that inserting the dielectric layer with annealing reduce the specific contact resistance of N-type germanium with metal and the Schottky barrier height. The experiment process contains ion implant, atomic layer deposition, Electron Beam Evaporation, RTA and MWA annealing, which can accurately simulate the source/drain situation in MOSFET.
The first part, phosphorous was implanted into the germanium at 150°C, followed by a low power microwave annealing and rapid thermal annealing. With the TEM and four-point probe, it is found that the doping of phosphorus ions can be effectively activated by the rapid thermal annealing at 450°C for 10 seconds and the low power microwave annealing at 1200W for 75 seconds. The two annealing recipes make non-crystal state Ge recover to crystal state with the resistance of less than 63 ohm/sq and 62 ohm/sq, which achieve solid phase epitaxial recrystallization (SPER). Therefore, RTA 450°C and MWA 1200W are selected as annealing conditions.
The second part, the use of dielectric layer insertion process, use Al2O3 and TiO2 as dielectric layer, observe the specific contact resistance and the Schottky barrier height by changing the thickness of the dielectric layer. Then analyzing it with J-V, I-T and TLM electrical measurement, it can be found that when the thickness of Al2O3 and TiO2 are 2 nm and 6 nm respectively can get to the lowest Schottky barrier height and to the lowest specific contact resistance. It is also found that TiO2 has the better ability to reduce the Schottky barrier height and the specific contact resistance than Al2O3, because TiO2 and Ge has lower conduction band offset, which reduces the Schottky barrier in addition to a smaller tunneling resistance can be achieved, so that have a larger current flow. Observing the different thicknesses of TiO2 when inserting to the device, it also can be found that the Schottky barrier height when the thickness of TiO2 dielectric layer decreases. As the result, it is concluded that the device inserted dielectric layer mainly modulate the Schottky barrier height by changing the position.
The third part, this paper discusses the influence of different annealing ways on the insertion of 2nm Al2O3 and 6nm TiO2. The experiment results show that the Schottky barrier height of Al2O3 and TiO2 are 0.4 eV and 0.18 eV respectively under the rapid thermal annealing, and the Schottky barrier height are 0.35eV and 0.14eV under the microwave annealing. While the specific contact resistance decreases an order, found that using microwave annealing can get a lower specific contact resistance and Schottky barrier height. Using C-V and G-V measured interface trap state density. The experiment results show that the Dit of Al2O3 and TiO2 are 3.31x1013 cm-2 eV-1 and 2.48x1013 cm-2 eV-1 respectively under the rapid thermal annealing, and the Dit are 7.45x1012 cm-2 eV-1 and 4.88x1012 cm-2 eV-1 under the microwave annealing. It is because microwave annealing is different from the rapid thermal annealing. Microwave annealing is characterized by its optical, penetrability and non-ionizing properties. In optical part, microwave is more able to propagate and concentrate like a ray of light than the low frequency radio waves, and does not become weaker because of the distance. In penetrability part, microwave irradiation is easier to penetrate into the material that makes microwave have better penetrability. In non-ionized part, when the quantum energy of the microwave interacts with the material, it does not change the internal structure of the material molecule (it only change its rotational state).
In this thesis, the physical mechanism of the Schottky barrier height is reduced by inserting the dielectric layer, and the thickness and the effect are explained. In addition, the change of the Schottky barrier height and the specific contact resistance under different annealing methods is compared and the optimum annealing mode, annealing energy, dielectric layer type and dielectric layer thickness are obtained. This method is very promising for short channel Ge NMOSFET.

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