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研究生: 柯盛瀚
Ke, Sheng-Han
論文名稱: 用於智慧虛實系統之高非揮發性記憶體壽命兼顧能量效益之非揮發性微處理器
High Nonvolatile Memory Endurance and Energy Efficiency Nonvolatile Processor for Cyber Physical System Applications
指導教授: 邱瀝毅
Chiou, Lih-Yih
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2016
畢業學年度: 104
語文別: 中文
論文頁數: 70
中文關鍵詞: 非揮發性微處理器獵能技術耗損平均技術系統壽命電阻式記憶體
外文關鍵詞: Nonvolatile processor, Energy harvesting, Wear-leveling, System endurance enhancement, Resistive RAM
相關次數: 點閱:87下載:7
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  • 隨著電腦的運算能力增強以及網路頻寬的加大,加速智慧虛實系統的發展,全世界即將邁入第四次工業革命又稱工業4.0。新型態的非揮發性微處理器系統其特性剛好最符合智慧虛實系統的需求,傳統的非揮發性微處理器研究總是只針對其硬體缺點下去進行架構優化,而未考量到其應用情境跟在上面運行的程式,導致總是改善了其中一個缺點卻產生了另一個問題。現在非揮發性微處理器的電源大量採用獵能技術,因此能量效率也是考量的重點之一。本論文提出針對系統耐用度提升同時兼顧其能量效率的新形態非揮發性微處理器系統架構,加入了冗餘動作削減技術及區塊位置重新分配兩種新技術,以類似耗損平均技術的方法,成功提升其耐用度及維持能量效率,又加入自適應性閥值調節技術來確保不同的應用情境可以維持其機制效果。經過本論文的設計優化後的非揮發性微處理器系統更符合智慧虛實系統其應用情境的設定。本論文所提出的架構與傳統的架構相比其耐用度提升25.9倍,不過能量效率只有1.5%的損失。其非揮發性微處理器性能指標相較於傳統架構有8.14倍的提升。

    Cyber Physical System is developing rapidly for Industry 4.0 applications because the enhancement of energy-efficient computing speed and improvement of internet bandwidth in recent years. A novel processor called Nonvolatile Processor has great potential to be the solution of Cyber Physical System because of its special features like zero standby power and resilience of power failure. Recent researches of Nonvolatile Processor (NVP) only consider the optimization of hardware, which fix problems related to its nonvolatile part, but not consider interaction with the application program and the environment that overlooks opportunities for further energy-efficient optimization. Energy efficiency is one of important factors for NVP because the NVP often adopts energy harvesters as power source. We proposed two novel techniques for the NVP with high system endurance also while maintaining energy efficiency. When compared to the state-of-the-art architecture, the proposed techniques increase endurance up to 25.9 times with as little as 1.5% energy overhead. Figure of merits (FoM) of the proposed NVP scores by 8.14 times higher than that of the compared architecture.

    目錄 i 表目錄 iii 圖目錄 iv 第 1 章 緒論 1 1.1 研究概觀 1 1.1.1 生醫智慧虛實系統 3 1.1.2 獵能技術 5 1.1.3 非揮發性微處理器 8 1.1.4 耗損平均技術 11 1.2 研究動機 13 1.3 研究貢獻 15 1.4 論文架構 16 第 2 章 相關背景與文獻 17 2.1 相關文獻探討 17 2.1.1 硬體層級實現方法 17 2.1.2 軟體層級實現方法 20 2.1.3 軟硬體交互參照層級方法 24 2.2 基準MSP430之非揮發性微處理器架構簡介 28 第 3 章 非揮發性微處理器設計 29 3.1 問題描述 29 3.1.1 冗餘儲存動作 29 3.1.2 損耗不平均 30 3.2 冗餘動作削減技術 32 3.3 區塊位置重新分配 34 3.3.1 冷熱區塊交換方法 35 3.3.2 多重熱區塊問題 38 3.3.3 多重冷區塊問題 40 3.4 非揮發性系統控制器整體架構 43 第 4 章 實驗結果與分析 46 4.1 實驗驗證平台 46 4.2 實驗一 非揮發性微處理器特性實驗 48 4.2.1 環境設定 48 4.2.2 系統儲存與恢復操作時間分析 49 4.2.3 備份動作操作能量消耗分析 50 4.2.4 系統能量效率分析 51 4.2.5 額外面積代價分析 52 4.2.6 非揮發性微處理器性能指標[20] 53 4.3 實驗二 智慧虛實系統應用情境實驗 55 4.3.1 環境設定 55 4.3.2 應用程式情境 55 4.3.3 實驗二之A 系統耐用度分析 57 4.3.4 實驗二之B 系統對抗電源喪失能力分析 58 4.4 實驗三 自適應性閥值調節技術實驗 60 4.4.1 問題介紹及環境設定 60 4.4.2 自適應性閥值調節技術 60 4.4.3 系統耐用度提升比例分析 62 4.4.4 非揮發性微處理器性能指標 63 第 5 章 結論與未來研究方向 65 5.1 結論 65 5.2 未來研究方向 66 參考文獻 67

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