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研究生: 顏年秀
Yen, Nien-Hsiu
論文名稱: AVC/H.264視訊編解碼器之去區塊效應濾波器架構設計
Architecture Design of De-blocking Filter in AVC/H.264 Video Codec
指導教授: 李國君
Lee, Gwo Giun
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2011
畢業學年度: 99
語文別: 英文
論文頁數: 110
外文關鍵詞: H.264, AVC, de-blocking filter, architecture, in-loop filter
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  • 此論文提供一種基於AVC/H.264視訊編解碼器之去區塊效應濾波器架構設計,其支援圖框式/圖場式之圖片可調性編碼,以及圖框式/圖場式之巨集方塊可調性編碼。基於自上至下設計方法論,將去區塊效應濾波演算法進行複雜度分析,以觀察在嚴苛情況下濾波器處理元件的平行度與系統工作頻率相應關係,並且以不同大小的資料精度為資料處理單位來進行設計空間探索,以觀察尖峰頻寬與記憶體需求相應關係。透過這些觀察,可基於工作頻率來決定濾波器處理元件的平行度,以維持濾波器處理元件之使用效率,且權衡尖峰頻寬與記憶體需求,選擇適當資料精度作為資料處理單位。
    接著,基於去區塊效應濾波演算法中資料相依性,在對應所訂資料精度之區塊內探索不同邊緣處理順序所對應之資料流,從資料流也可觀察相應之硬體需求。因此,考量系統工作頻率、相應之硬體需求及資料的可重複使用性,從而決定適當的邊緣處理順序,及發展符合應用需求之去區塊效應濾波器架構設計。此去區塊效應濾波器架構設計為基於解碼器系統而發展,亦考量了其與相關模組之間的介面與資料溝通。

    This thesis provides an architectural design filter in AVC/H.264 video codec, which supports the picture-adaptive field/frame mode and the macroblock-adaptive field/frame mode. Using a top-down design methodology, complexity analysis on the de-blocking filter algorithm was done to find a relation between the parallelism of the processing element (PE) of the de-blocking filter and the system operation frequency in a critical condition. Design space exploration was performed on different data granularities to determine a relation between the peak bandwidth and memory requirement. The parallelism of the PE can be determined based on the system operation frequency for maintaining the usage efficiency of the PE. A proper data granularity can be selected to serve as a data unit for processing, by striking a compromise between peak bandwidth and memory requirement.
    In addition, based on data dependency of the de-blocking filter algorithm, data flow corresponding to different processing orders of edge in a block corresponding to the determined data granularity was explored. From the data flow, the corresponding hardware requirements could be determined. Hence, with consideration of the system operation frequency, the corresponding hardware requirement, and data reuse, the proper processing order of edge is further determined, and the de-blocking filter architecture design is developed to conform to an application requirement. The architectural design of the de-blocking filter is developed based a decoder system. Interfaces and data communication between the de-blocking filter architecture and each related module were also taken into consideration.

    Abstract ii Table of Contents iv List of Figures vi List of Tables ix Chapter 1. Introduction 1 1.1 Background 1 1.2 Motivation 2 1.3 Organization o the thesis 3 Chapter 2. Algorithm of De-blocking Filter in AVC/H.264 4 2.1 Cause of Blockiness 5 2.2 Processing Order of Edge 6 2.3 Boundary Strength Determination 7 2.3.1 Boundary Strength for Luminance 7 2.3.2 Boundary Strength for Chrominance 9 2.4 Filtering Process 12 2.4.1 Filtering Process of BS = 1, 2, or 3 14 2.4.2 Filtering Process of BS = 4 15 2.5 Sample Location for Boundary Edge 17 2.5.1 Sample Location in Normal Mode 17 2.5.2 Sample Location in MBAFF Mode 19 Chapter 3. Proposed Architecture Design of De-blocking Filter in AVC/H.264 26 3.1 Reconfigurable Video Coding (RVC) Decoder 27 3.1.1 Application Specification 27 3.1.2 Top Level Block Diagram 29 3.2 Complexity Analysis of De-blocking Filter Algorithm in AVC/H.264 36 3.2.1 Number of Operation 36 3.2.2 Total Operation for Real-Time Process 42 3.3 Design Space Exploration of De-blocking Filter in AVC/H.264 49 3.3.1 Data Granularity 50 3.3.2 Comparison of Data Granularity 72 3.3.3 Processing Order 75 3.4 Implementation of Architecture Design 82 3.4.1 Top-Level Block Diagram of the De-blocking Filter Architecture 83 3.4.2 Data Flow 87 3.4.3 Block Diagram of Proposed Architecture 95 3.4.4 Internal Memory Organization 100 Chapter 4. Verification 104 Chapter 5. Conclusion and Future Work 106 5.1 Conclusion 106 5.2 Future Work 107 Reference 108

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