| 研究生: |
黃建智 Huang, Chien-Chih |
|---|---|
| 論文名稱: |
應用於BGV全同態加密之可重組非二次冪之數論轉換架構設計 A Reconfigurable VLSI Architecture of Non-Power-of-Two Number Theoretic Transform for BGV Fully Homomorphic Encryption |
| 指導教授: |
謝明得
Shieh, Ming-Der |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2022 |
| 畢業學年度: | 110 |
| 語文別: | 英文 |
| 論文頁數: | 53 |
| 中文關鍵詞: | 全同態加密 、多項式乘法 、互質因子算法 、雷德演算法 、混合基數定址演算法 |
| 外文關鍵詞: | Fully Homomorphic Encryption, Polynomial multiplication, Prime-factor FFT Algorithm, Rader's FFT Algorithm, Mixed-radix Memory Addressing Algorithm |
| 相關次數: | 點閱:136 下載:1 |
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全同態加密 (Fully Homomorphic Encryption, FHE) 允許直接對加密後的密文進行運算,可等同於對其未加密的明文進行相同的運算,從而保留雲端計算和數據隱私的雙重優勢。然而,全同態加密的安全性是建立在大量複雜的同態運算之上,因此在全同態加密成為普遍應用之前,許多人致力於降低同態運算的複雜度以及開發低複雜度的硬體加速器。本論文著重在低複雜度且可重組之非二次冪數論轉換 (Number Theoretic Transform, NTT) 架構設計,其主要應用於 BGV-FHE 方案中的多項式乘法運算,於同態乘法、密鑰交換 (key-switching)、模數交換 (modulus-switching) 以及重加密 (recryption) 等重要運算中皆會大量使用到多項式乘法運算。
本研究透過互質因子算法與雷德演算法遞迴拆解的優化方法可將大點數NTT透過分解成多個小點數運算來求得,進而得到較低的運算複雜度與記憶體需求量。以78881點NTT的應用為例,使用所提出之演算法所需的模乘法和模加法的數量相較於相關文獻之方法減少了約 3.13 和 2.75 倍。而在記憶體需求方面,隨機存取記憶體 (RAM) 與唯讀記憶體 (ROM)之需求量可分別減少到HElib所需之30%與0.047%。在硬體實現方面,採用所提出之可重組化運算元件 (Processing Element, PE),其執行NTT運算所需的週期(cycle)數與採用以8為底數(radix-8) 蝴蝶單元之布魯斯坦快速傅立葉轉換(Bluestein's FFT)相仿,對於大點數NTT如77531與78881而言,其記憶體面積的改善程度更加顯著,可分別減少到HElib所需之57% 和 63%。
Fully homomorphic encryption (FHE) basically allows the typical operations to be performed directly on the encrypted data, thus it successfully retains the actual benefits of cloud computing and data privacy. However, the security level of FHE is eventually built on a huge amount of complex homomorphic operations. More efforts should be devoted in order to reduce the complexity of homomorphic evaluation algorithms and developing low-complexity hardware accelerator before the pervasive applications of FHE. This work mainly focuses on the low complexity and reconfigurable NTT defined over non-power-of-two cyclotomic polynomial rings, that can be applied in polynomial multiplication, key-switching, modulus switching and bootstrapping processes in the BGV-FHE scheme.
The resulting complexity is optimized by applying the prime-factor factorization scheme followed by the iterative decomposition method. For example, when the 78881-th cyclotomic polynomial is being considered, about 3.13 and 2.75 times of improvement will be found in the total number of required modular multiplication and modular addition. In terms of hardware implementation, by adopting the proposed architecture, it can keep the cycle less than or equal to Bluestein’s FFT using radix-8 butterfly unit but the total memory area can be gradually reduced to 57% and 63% when adopting the 77531-th and 78881-th cyclotomic polynomials, respectively.
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