近代深度神經網路主要是基於機器學習的演算法，並發展出有如捲積神經網路(CNN)[1]、生成對抗神經網路(DCGANs)[2]等神經網路，廣泛的應用於人工智慧、圖像分類等領域。深度神經網路模型在應用中具有的顯著的準確性，但是大量的運算難以在資源有限的嵌入式硬體上執行；因此，對深度神經網路進行資料壓縮是必要的，藉此減少多餘不必要的資料，降低深度神經網路的運算量與硬體功耗。但是若以傳統儲存方式處理壓縮過後的資料將會造成多餘的記憶體儲存量，因此對於壓縮過後的資料以稀疏壓縮格式進行轉換並儲存以避免造成記憶體儲存過多冗餘的參數。此外，反捲積的資料訓練時使用的重複性高，相對的存取記憶體次數就多，因此在這種資料訓練時將會造成不必要功率消耗和計算延遲。
本論文針對反捲積(Deconvolution, DCNN)加速器架構進行設計，將深度神經網路中存在冗餘的稀疏權值藉由(Comprass Row Storage, CSR)壓縮編碼格式以該權值所在行、列和值的儲存方式將非零權值保存下來，藉此降低神經網路中的運算次數。除此之外，我們可以利用透過CSR方法保存下來的權值進行資料重複使用的設計，減少對記憶體的存取。
本文的實驗中，使用了Cyclone IV GX EP4CGX150DF31C7 FPGA板來表示加速稀疏反捲積的加速效果，從實驗數據得知，此架構能夠提升2.2倍的效能提升，並且降低大約80%的冗餘運算，且能減少對記憶體的存取進而降低整體的功耗。

In recent years, CNN accelerators have been proposed for optimizing then performance and power efficiency. However, there has been little research on the design of deconvolutional neural networks (DCNNs). In the conventional way of image deconvolution, the number of multiplications is very high. Thereby the computational complexity is also high. Weight prunning can compress DCNNs models by removing redundant parameters in the networks. Prunning can remove more than 80% of the parameters, it actually improve the performance. Two major problems cause this unsatisfactory performance on FPGA. First, DCNNs onto matrix multiplication reduces data reuse opportunities. Second, the sparsity brought by pruning makes the computation irregular, which leads to inefficiency when processing massively computational DCNNs. Evaluation on a Cyclone II FPGA board show that our acceleration can improve sparse deconvolution speedup by 2.2 and reduce at least 80% of MAC. DRAM access is critical for DCNNs performance as well as a major contributor to system energy consumption. minimizing the number of access external DRAM times can decline power consumption.

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