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研究生: 陳奕嘉
Chen, Yi-Jia
論文名稱: 應用於鋰離子電池供電裝置之具高速暫態響應無外接電容式低壓降電壓調節器
A Fast Transient Capacitor-Less Low Dropout Regulator for Li-Ion Battery-Powered Devices
指導教授: 劉濱達
Liu, Bin-Da
共同指導教授: 魏嘉玲
Wei, Chia-Ling
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 英文
論文頁數: 87
中文關鍵詞: 低壓降電壓調節器直流對直流調節器無外接電容式低壓降電壓調節器
外文關鍵詞: CL-LDO regulator, DC-DC regulator, LDO regulator
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  • 本論文提出一個可應用於鋰離子電池供電裝置且具備高速暫態響應能力之無外接電容式低壓降電壓調節器。所提出的無外接電容式低壓降電壓調節器以台灣積體電路公司0.18-µm一層多晶矽六層金屬導線互補式金屬氧化物半導體製程實現,而無外接電容式低壓降電壓調節器所占的晶片有效面積為0.054 mm2。
    所提出的無外接電容式低壓降電壓調節器可以在電源供應2.7至4.2 V的輸入電壓下,提供2.5 V的穩定輸出電壓。此外,所提出的無外接電容式低壓降電壓調節器即使在輸出負載電容高達100 pF的情況下,也能在0至100 mA的負載範圍內保持穩定輸出。藉由所提出的暫態響應增強技術的應用,使無外接電容式低壓降電壓調節器在只消耗7.2 μA的靜態電流下仍可達到高速暫態響應,並且具有高達99.92 %的最大電流效率。另一方面,所提出的無外接電容式低壓降電壓調節器在負載調節率、電壓調節率以及電源拒斥比等性能參數上也具有良好的表現。最後,與過去發表的文獻相比,所提出的無外接電容式低壓降電壓調節器更具有最佳的暫態響應特性與最小的晶片有效面積。

    This thesis presents a fast transient capacitor-less low dropout (CL-LDO) voltage regulator for Li-ion battery-powered devices. It has been implemented in TSMC 0.18-µm 1P6M CMOS technology and the active area of the proposed CL-LDO is 0.054 mm2.
    The proposed CL-LDO provides a regulated output voltage at 2.5 V while the power supply provides an input voltage ranging from 2.7 to 4.2 V. In addition, the proposed CL-LDO can remain stable under full load range from 0 to 100 mA even though the output loading is as high as 100 pF. With the application of the proposed transient-enhanced techniques, the proposed CL-LDO achieves fast transient response with quiescent current of 7.2 µA at no load condition, and the maximum current efficiency is 99.92 % at full load condition. Besides, the proposed CL-LDO also achieves good performance parameters in load regulation, line regulation and PSR. Finally, compared with previously published works, the proposed CL-LDO achieves the best transient figure-of-merit (FOM) and the smallest active area among the published works.

    Abstract (Chinese) i Abstract (English) iii Acknowledgement v Table of Contents vii List of Figures xi List of Tables xiii Chapter 1 Introduction 1 1.1 Research Background 1 1.2 Motivation 2 1.3 Organization of the Thesis 3 Chapter 2 Basic Concepts of Low Dropout Voltage Regulator 5 2.1 Operation Principles of Conventional LDOs 6 2.2 Definitions of Performance Parameters 8 2.2.1 Dropout voltage 8 2.2.2 Efficiency 10 2.2.3 Load regulation 11 2.2.4 Line regulation 11 2.2.5 Power supply rejection 12 2.3 Small-Signal Analysis of the Conventional LDO 13 2.4 Load Transient Response of the Conventional LDO 15 2.5 Fundamentals of CL-LDOs 17 2.5.1 Advanced compensation topologies 19 2.5.2 Load transient topologies 21 2.6 Fundamentals of Bandgap Voltage Reference 26 2.6.1 PSR analysis 27 2.6.2 Temperature compensation 29 Chapter 3 The Proposed Circuit Architecture 31 3.1 The Proposed CL-LDO Architecture 32 3.2 Stability Analysis 34 3.3 Quiescent Current Reduction 37 3.4 Transient Response Enhancement 38 3.4.1 Buffer stage 39 3.4.2 Adaptive biased circuit 39 3.4.3 Voltage spike detection circuit 42 3.5 Bandgap Voltage Reference 44 3.5.1 Bandgap core 45 3.5.2 PSR enhancement stage 46 3.5.3 Frequency compensation 48 3.5.4 Bias and start-up circuit 49 Chapter 4 Experimental Results and Discussion 51 4.1 Simulation Results 52 4.1.1 Layout 52 4.1.2 Loop stability 54 4.1.3 Load transient response 55 4.1.3 Load regulation 57 4.1.4 Line regulation 58 4.1.5 Power supply rejection 59 4.1.6 Performance summary 60 4.2 Measurement Results 61 4.2.1 Measurement environment 62 4.2.2 Load transient response 63 4.2.3 Load regulation 70 4.2.4 Line regulation 71 4.2.5 Power supply rejection 72 4.2.6 Quiescent current and current efficiency 74 4.3 Comparison and Discussion 76 Chapter 5 Conclusion and Future Work 79 5.1 Conclusion 80 5.2 Future Work 81 References 83 Biography and Awards 87

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