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研究生： 黃瑞祥
Huang, Reui-Siang
論文名稱： 適用於微處理器之低功率多工存取埠暫存器檔案電路設計與實現
Design and Implementation of a Low-Power Multi-Port Register File for Microprocessors
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2006
畢業學年度： 94
語文別： 英文
論文頁數： 71
中文關鍵詞： 暫存器檔案 、漏電流功率消耗
外文關鍵詞： register file, leakage power
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    • 　　在近代的微處理器中，暫存器檔案電路是主要的核心儲存元件且會有大量的功率消耗。我們提出一種新型態儲存細胞架構用來切斷漏電流路徑以達到減少漏電流所造成之功率消耗。在本論文中，四寫入埠、八讀出埠、容量為32 x 32位元之暫存器檔案電路被設計及實現在TSMC 0.18μm CMOS製程之下，用來評估在不同儲存細胞架構下的電路速度及功率消耗。應用我們所提出的新型態儲存細胞所建立之多工存取埠暫存器檔案電路證明能有效的在功率消耗上獲得改善。模擬的結果得知與傳統的儲存細胞架構相比，在儲存細胞陣列上的漏電流功率消耗可減少22%。使用我們的儲存細胞架構，在資料寫入週期內的操作速度能提升1.67倍。此外，在儲存細胞陣列上的動態功率消耗也可減少70%。

    　Register file is the kernel storage element on the modern microprocessor and consumes significant amount of power. We propose a novel storage cell structure which cuts off the leakage path to reduce leakage power consumption. This thesis designs and implements 4-write-port, 8-read-port 32 x 32-bit register files by using TSMC 0.18μm CMOS technology for different storage cell structures to evaluate the performance in speed and power consumption. The proposed storage cell built in the multi-port register file architecture demonstrates significant improvement in power consumption. The simulated results show that the leakage power in the storage cell array is reduced by 22% while comparing with the conventional storage cell structure. Using our storage cell, the operating speed in data writing period can be improved by 1.67X. Moreover, the dynamic power consumption can be reduced by 70% in the storage cell array.

    Chapter 1 Introduction...............................1 1.1 Motivation.....................................1 1.2 Organization of the Thesis.....................2 Chapter 2 Low Power Circuit Techniques...............3 2.1 Source of Power Consumption....................3 2.2 Overview.......................................4 2.3 Dynamic/Active Power Consumption...............4 2.3.1 Supply Voltage Scaling....................5 2.3.2 Power Gating..............................6 2.3.3 Effect Capacitance Reduction..............7 2.3.4 Operating Frequency Scaling...............7 2.3.5 Switching Activity Reduction..............7 2.4 Standby/Leakage Power Consumption..............8 2.4.1 MTCMOS...................................10 2.4.2 VTCMOS...................................11 2.4.3 Stack Effect.............................12 2.5 Summary.......................................12 Chapter 3 Low Power Regiser File Design.............14 3.1 Overview of Register File.....................14 3.2 Basic Storage Cell............................17 3.3 Design Consideration..........................17 3.3.1 Active Power Consumption.................17 3.3.2 Leakage Power Consumption................17 3.3.3 Operating Speed..........................18 3.3.4 Stability................................19 3.3.5 Temperature..............................22 3.4 Multiple Access Port Design...................24 3.4.1 Multi-Port Read Operation................24 3.4.2 Multi-Port Write Operation...............24 3.4.3 Power Dissipation in Write Operation.....28 3.5 Storage Cell Design...........................29 3.5.1 Voltage Scaling..........................29 3.5.2 Dual-Vth Cell............................29 3.5.3 Dynamic-Vth Cell.........................30 3.5.4 Gated Vdd/Ground.........................31 3.5.5 Data Retention Gated-Ground Cache........32 3.5.6 Strong Inverter..........................32 3.5.7 Transmission Gate........................33 3.6 Decoder.......................................34 3.6.1 Overview of Decoder......................34 3.6.2 Design Issues............................35 3.6.2.1 Elmore Delay.........................35 3.6.2.2 Sizing of Buffer.....................36 3.6.3 Decoder Design for Low Power consumption.37 3.6.3.1 DWL..................................37 3.6.3.2 Conventional Circuit.................38 3.7 Sense Amplifier...............................39 3.7.1 Differential-Ended Sense Amplifier.......40 3.7.2 Single-Ended Sense Amplifier.............42 3.8 Sense Enabling Signal.........................42 3.8.1 Address Transition Detection (ATD).......43 3.8.2 Replica Circuit..........................44 3.9 Summary.......................................44 Chapter 4 Novel Low Power Multi-Port Register File..46 4.1 Novel Low Leakage Storage Cell................46 4.1.1 Novel Storage Cell Structure.............48 4.1.2 Improved Storage Cell Architecture.......49 4.2 Enhamced Sense Amplifier......................54 4.2.1 Voltage Controlled Buffer................55 4.3 Split Decoder Scheme..........................56 4.4 Implementation of Register File...............58 4.5 Summary.......................................63 Chapter 5 Conclusions and Future work...............64 5.1 Conclusions...................................64 5.2 Future Work...................................65 References..........................................66

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