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研究生： 黃俊博
Huang, Chun-Po
論文名稱： 連續逼近式類比數位轉換器之設計自動化與錯誤分析
Design Automation and Error Analysis for Successive Approximation Register Analog-to-Digital Converters
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 132
中文關鍵詞： 連續逼近式類比數位轉換器 、設計方法 、設計自動化 、錯誤分析
外文關鍵詞： Successive approximation register (SAR) analog-to-digital converter (ADC), design methodology, design automation, error analysis
相關次數： 點閱：224  下載：27 
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    • 由於擁有良好的能量消耗效率，連續逼近式類比數位轉換器近年來被廣泛地使用在生醫與可攜式/穿戴式電子裝置上。然而即使是經驗豐富的電路設計者，設計一個連續逼近式類比數位轉換器並對其最佳化，也是一件相當耗時的工作。而對於系統設計者而言，針對連續逼近式類比數位轉換器，也很難快速地在某個製程條件下評估一個規格的可行性。藉由人工設計所歸納出的經驗，我們在本論文中針對連續逼近式類比數位轉換器提出了一套系統化的設計流程。再根據這套設計流程，實現了一個元件尺寸制定的軟體工具，其成果與近期文獻發表的成品相比仍具有相當的競爭力，而且因為依電路特性個別使用了適當的搜尋演算法，所以軟體執行的時間也相對的短。除了模擬結果，本論文亦含括三個不同規格與製程的晶片來展示這個設計方法的可行性。
    在本論文中，我們也針對連續逼近式類比數位轉換器的一些錯誤來源作了完整的研討。探討的錯誤來源包含比較器的偏移，以及電容式數位類比轉換器的動態增益誤差、電容不匹配、電位轉移未達穩定、參考電壓的抖動，最後是輸入訊號造成的牽引干擾。我們說明並分析了造成此類比數位轉換器的微分非線性誤差與積分非線系誤差，並以這兩項非線性誤差為基礎歸納出一個辨認可能誤差來源的偵測流程。除此之外，我們也在本論文內提供了一些能克服這些誤差來源的設計建議。

    Successive approximation register (SAR) analog-to-digital converters (ADCs) are widely used in biomedical and portable/wearable electronic systems due to their excellent energy efficiency. However, both the design and the optimization of high-performance SAR ADCs are time consuming, even for well-experienced circuit designers. For system designers, it is also difficult to quickly evaluate the feasibility of realizing a SAR ADC for a given specification in a specified process node. This dissertation presents a systematic device sizing procedure for SAR ADCs based on designer experiences. A sizing tool based on the proposed design procedure is also implemented. Experimental results show that the generated SAR ADCs are highly competitive to many recently published works. Moreover, by employing the appropriate search algorithms according to the circuit characteristic, the sizing time is relatively short. In addition to the simulation results, three silicon proofs with different specifications and process nodes are provided to demonstrate the feasibility of this design methodology.
    Besides, a comprehensive investigation on several important error sources for the SAR ADCs is also presented in this dissertation. The error sources investigated here include the dynamic comparator offset, the dynamic gain error of digital-to-analog converter (DAC), the capacitor mismatch of capacitive DAC, the incomplete settling of DAC, the undershoot of reference voltage, and the input signal coupling. The integral/differential non-linearities (INL/DNL) of SAR ADCs those are resulted from these error sources are analyzed and addressed. A diagnosis procedure is presented to identify the possible error sources based on the INL/DNL plots. In addition, design suggestions for overcoming these problems are also recommended in this dissertation.

    中文摘要 III Abstract V List of Tables XII List of Figures XIII List of Abbreviations XVIII Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Dissertation 5 Chapter 2 Background Knowledge of SAR ADCs 6 2.1 Architecture 6 2.2 Operation Phases 8 2.2.1 Sampling Phase 8 2.2.2 Bit-conversion Phase 9 2.3 Design Considerations 13 2.3.1 Comparator 13 2.3.2 Sample-and-Hold (S/H) Circuit 16 2.3.3 Digital-to-Analog Converter (DAC) 20 2.3.4 SAR Control Logic 22 Chapter 3 Design Methodologies of SAR ADCs 23 3.1 Previous Work and Our Contribution 23 3.1.1 Previous Work 23 3.1.2 Our Contribution 24 3.2 Overview of Sizing Procedure 26 3.2.1 Specification and Process Data 27 3.2.2 Time Budget of Comparator 28 3.2.3 Sizing of the Remaining Building Blocks 28 3.2.4 Optimization 29 3.2.5 Tradeoff between Different Blocks 29 3.3 Design Methodologies 30 3.3.1 Comparator 30 3.3.2 S/H Circuit 36 3.3.3 DAC 38 3.4 Exploration of Solution Space 41 Chapter 4 Sizing Results 45 4.1 A 10-bit 20 MS/s Synchronous SAR ADC 47 4.2 A 10-bit 100 MS/s Asynchronous SAR ADC 51 4.2.1 Comparison with Other Manual State-of-the-Art Works 51 4.2.2 Execution Time Analysis 54 4.2.3 Silicon Proof 55 4.3 A 12-bit 600 kS/s SAR ADC for Bio-medical application 60 4.3.1 Introduction to Potentiostat 60 4.3.2 System Architecture and Operations 62 4.3.3 Experimental Results 67 Chapter 5 Analysis of Non-idealities of SAR ADCs 79 5.1 Error Sources in Comparator 80 5.1.1 Static Offset 80 5.1.2 Dynamic Offset 81 5.2 Error Sources in DAC 86 5.2.1 Static Gain Error and Dynamic Gain Error 87 5.2.2 Capacitor Mismatch 92 5.2.3 DAC Incomplete Settling 93 5.2.4 Undershoot of Reference Voltage 95 5.2.5 Input Signal Coupling 96 5.3 Experimental Results 98 5.3.1 Dynamic Offset 98 5.3.2 Dynamic Gain Error 100 5.3.3 Capacitor Mismatch 102 5.3.4 DAC Incomplete Settling 104 5.3.5 Undershoot of Reference Voltage 105 5.3.6 Input Signal Coupling 107 5.3.7 Check Flow and Multiple Errors Example 108 5.4 Summary 111 Chapter 6 Concluding Remarks and Future Work 112 6.1 Concluding Remarks 112 6.2 Future Work 113 Bibliography 114 Appendix 121 Appendix.1 121 Appendix.2 122 Appendix.3 123 Appendix.4 124 Publication List 128

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