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研究生：	方俊翰 Fang, Chun-Han
論文名稱：	基於低成本單晶片系統除錯平台之適用於實際工業界應用之完整除錯流程 Complete Debug Procedures for Realistic Industrial Applications Based on A Low-Cost On-Chip SoC Debug Platform
指導教授：	李昆忠 Lee, Kuen-Jong
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2010
畢業學年度：	98
語文別：	英文
論文頁數：	69
中文關鍵詞：	單晶片、除錯
外文關鍵詞：	SoC, debug
相關次數：	點閱：61 下載：0
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隨著製程技術與設計自動化工具的快速演進，越來越多大型且複雜的電路被整合進系統單晶片。對於複雜的系統單晶片而言，即使以軟體為基礎的模擬方式驗證成功，也無法確保實際晶片是否能正常運作。因此，在產品開發的過程中，設計者常常在除錯與驗證實際晶片的階段耗費大量時間，極有可能造成產品上市時間的延誤。為了能有效節省晶片除錯及驗證的時間，晶片設計者需要一個有效且系統化的除錯方式。
　　在本論文中，我們以成大測試實驗室所開發的單晶片系統除錯平台為基礎，致力於將此除錯平台與業界實際環境整合。將此除錯平台整合至業界的系統單晶片環境之後，再以業界實際的矽智產電路做為除錯對象，並實現在業界的雛型驗證版上。我們也將此平台與 ARM 處理器以及 ARM CoreSight on-chip debug and trace architecture 結合，提出嶄新的除錯流程，使除錯功能更加完整。此外，我們亦結合使用者圖形介面來與此除錯平台共同運作，提供波形化顯示的方式，使用者將可更容易地觀察連續時間的硬體擷取結果，以判別實際晶片中錯誤的根本原因。實驗結果顯示所開發的除錯平台應用到業界實際電路的可行性，能有效地解決晶片的除錯問題，加速業界產品的開發過程。

With the rapid development of semiconductor technology and design automation tools, more and more designs are now integrated into a so-called system-on-a-chip (SoC). For a complicated SoC, even if we verify the designs by software-based simulation thoroughly, we still cannot assure that the real chips can work without any bug. Hence, designers usually spend much time in debugging and verifying the real chip in the developing process, which often results in the delay of time-to-market. To overcome this problem, chip designers need not only efficient but also systematic debugging architectures and procedures.
In this thesis, we integrate the SoC debug platform developed by the NCKU Test Lab with a real industrial SoC design environment. After the integration, we employ an actual industrial intellectual property (IP) core as the core under debug and then implement the whole SoC system on an industrial prototyping board. We also combine the debug platform with an ARM processor and the ARM CoreSight on-chip debug and trace architecture, and propose novel debug procedures which make the debugging functions complete and efficient. Furthermore, we combine a graphic user interface with the debug platform to support the waveform-based display which allows users to observe the successive traced results of hardware easily to identify the root-cause of failures in the real chip. Experimental results show that the developed debug technology not only deals with the chip debugging problems efficiently but also accelerate the developing process of industrial products.

TABLE OF CONTENTS

Chapter 1 Introduction	1
1.1 Motivation	1
1.2 Overview of Thesis	2
1.3 Organization	4
Chapter 2 Background & Previous Work	6
2.1 Background	6
2.1.1 SoC Test Platform	6
2.1.2 SoC Debug Platform	9
2.1.3 ARM ICE	11
2.1.4 ARM CoreSight On-Chip Debug and Trace Architecture	12
2.2 Previous Work	14
2.2.1 Processor-Based Debug	15
2.2.2 SoC Platform-Based Debug	16
2.2.3 ECT-Based Debug	19
Chapter 3 Debug Procedures	21
3.1 Stage1: Check the System Environment	22
3.2 Stage2: Check the Setting of the CUD	23
3.3 Stage3: Check the Operation of the CUD	25
Chapter 4 Implementation of SoC Debug Platform	26
4.1 Overall Architecture of SoC Debug Platform	26
4.2 Hardware Components of SoC Debug Platform	28
4.2.1 TAM Controller	28
4.2.2 Setup Registers	31
4.2.3 Hardware Breakpoint Mechanism	36
4.2.4 Local Memory Mechanism	40
4.2.5 Integration with the CSCTI Module	42
4.3 Software Components of Debug Platform	43
Chapter 5 Case Study	45
5.1 SoC Debug Platform with JPEG decoder	45
5.2 Simulation Environment	47
5.2.1 Architecture	47
5.2.2 Memory Mapping Address Allocation	48
5.2.3 Simulation Results	50
5.3 Emulation Environment	53
5.3.1 FPGA Prototyping	53
5.3.2 Graphic User Interface (GUI)	56
5.3.3 Emulation Results	61
Chapter 6 Conclusions and Future Work	64
6.1 Conclusions	64
6.2 Future Work	65
References	66





















LIST OF FIGURES
FIGURE 2 1 OVERVIEW OF TEST PLATFORM	8
FIGURE 2 2 OVERVIEW OF SOC DEBUG PLATFORM	10
FIGURE 2 3 ARM DEBUG SYSTEM	12
FIGURE 2 4 AN EXAMPLE OF CORESIGHT DEBUGGING ENVIRONMENT	13
FIGURE 2 5 CTM AND CTI BLOCK DIAGRAM	14
FIGURE 2 6 IEEE 1149.1 JTAG SUPPORT DEBUG ARCHITECTURE	16
FIGURE 2 7 DSP PLATFORM DEBUG INTERFACE	18
FIGURE 2 8 CORE-BASED SCAN ARCHITECTURE	19
FIGURE 2 9 BREAKPOINT GENERATION AND DISTRIBUTION ARCHITECTURE IN [19]	20
FIGURE 3 1 STAGE 1 OF DEBUG PROCEDURES	23
FIGURE 3 2 STAGE 2 OF DEBUG PROCEDURES	24
FIGURE 3 3 STAGE 3 OF DEBUG PROCEDURES	25
FIGURE 4 1 OVERALL ARCHITECTURE OF SOC DEBUG PLATFORM	27
FIGURE 4 2 ARCHITECTURE OF TAM CONTROLLER	29
FIGURE 4 3 DATA FIELD OF VALID SETUP REGISTER	33
FIGURE 4 4 DATA FIELD OF TMS SETUP REGISTER	34
FIGURE 4 5 DATA FIELD OF TAM CONTROLLER SETUP REGISTER	34
FIGURE 4 6 DATA FIELD OF BKT_CNT_EN SETUP REGISTER	35
FIGURE 4 7 DATA FIELD OF CLOCK CONTROL SETUP	36
FIGURE 4 8 GLITCH PREVENTION FOR CLOCK GATING	37
FIGURE 4 9 CLOCK GATING MECHANISM IN THIS WORK	38
FIGURE 4 10 TIMING DIAGRAM OF CLOCK GATING MECHANISM	39
FIGURE 4 11 HOLD CONTROL UNIT	40
FIGURE 4 12 LOCAL MEMORY MECHANISM	41
FIGURE 4 13 TAMC_INTERFACE MODULE	42
FIGURE 4 14 INTEGRATION WITH THE CSCTI MODULE	43
FIGURE 4 15 SOFTWARE PROGRAM	44
FIGURE 5 1 SOC DEBUG PLATFORM WITH JPEG DECODER	47
FIGURE 5 2 SIMULATION ENVIRONMENT OF SOC DEBUG PLATFORM	48
FIGURE 5 3 SIMULATION RESULTS OF JPEG FUNCTION	50
FIGURE 5 4 SIMULATION RESULTS OF CSCTI MODULE	50
FIGURE 5 5 SIMULATION RESULTS OF TAMC INTERFACE	51
FIGURE 5 6 SIMULATION RESULTS OF SUSPEND MECHANISM	52
FIGURE 5 7 SIMULATION RESULTS OF RESTORE MECHANISM	53
FIGURE 5 8 EMULATION ENVIRONMENT OF SOC DEBUG PLATFORM	54
FIGURE 5 9 FPGA PROTOTYPE SYSTEM FOR THIS WORK	55
FIGURE 5 10 OVERVIEW OF GRAPHIC USER INTERFACE	57
FIGURE 5 11 MENU OF “PROJECT”	57
FIGURE 5 12 MENU OF “DEBUG PLATFORM”	57
FIGURE 5 13 SETUP WINDOW OF MCD HARDWARE BREAKPOINT INSERTION	58
FIGURE 5 14 CONTROL AND DISPLAY WINDOW	59
FIGURE 5 15 WAVEFORM-BASED DISPLAYS OF TRACED DATA	60
FIGURE 5 16 AN EXAMPLE OF JPG FILES	61
FIGURE 5 17 MEMORY VIEW OF REALVIEW DEBUGGER	62
FIGURE 5 18 CHECK THE SETUP REGISTER OF JPEG DECODER IN EMULATION	62
FIGURE 5 19 CHECK THE OPERATION OF JPEG DECODER IN EMULATION	63
FIGURE 5 20 AN EXAMPLE OF YUV FILE	63

 
LIST OF TABLES
TABLE 4 1 SETUP REGISTERS IN THE TAM CONTROLLER	32
TABLE 5 1 MEMORY MAPPING ADDRESS ALLOCATION	49
 


                                    

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[2] Altera Corp., Design Debugging Using the SignalTap II Embedded Logic Analyzer, http://www.altera.com.

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[15] ARM Ltd. Web Site, http://www.arm.com.

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校內：2015-08-30公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

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