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研究生： 蔡肇芳
Tsai, Chao-Fang
論文名稱： 一個十位元每秒一億次取樣的高功率效率複合式類比數位轉換器
A 10-bit 100-MS/s Power-Efficient Flash SAR ADC
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 英文
論文頁數： 63
中文關鍵詞： 轉換器
外文關鍵詞： Subrange ADC
相關次數： 點閱：65  下載：9 
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    • 於本論文中，我們實現了一個十位元每秒一億次取樣的高效率複合式類比數位轉換器。我們使用了分散單調式電容切換的機制，可以有效地控制比較器的動態偏移量。除此之外，我們加入了二進制的錯誤補償機制，以提升類比數位轉換器的操作速度。再者，我們使用的電阻性和電容性的DAC，可以省下約50%的電容量。本設計使用台積電 90奈米製程設計。模擬結果顯示在一億次的取樣頻率下，有效位元數為9.88位元，消耗功率為2.18 mW。有效信號頻寬為二億赫茲。每一次資料轉換消耗 23.3 fJ。

    In this thesis, we propose a 10-bit 100-MS/s power-efficient flash SAR ADC. In order to reduce the signal-dependent dynamic offset of the comparator, we use the splitting monotonic switching method to decrease the comparator input common-mode voltage change. In addition, we add redundancy capacitors to improve the settling issue. We also use a resistive/capacitive hybrid DAC instead of a purely capacitive one. With this method, we save about 50% unit capacitors of the DAC. The proposed ADC is designed in TSMC 90-nm. In the post-simulation, the ENOB is 9.88 bit with 100-MHz sampling speed. The power consumption is around 2.18 mW. The resultant FOM is 23.3 fJ/conversion-step.

    List of Figures IX List of Tables XI Chapter 1 Introduction 1 1.1 MOTIVATION 1 1.2 ORGANIZATION 3 Chapter 2 Analog-to-Digital Converter 4 2.1 INTRODUCTION 4 2.2 ADC PERFORMANCE METRICS 5 2.2.1 Resolution 6 2.2.2 Accuracy 6 2.2.3 Static Specifications 6 2.2.4 Dynamic Specifications 9 2.3 ADC ARCHITECTURES 13 2.3.1 Flash Architecture 14 2.3.2 Pipelined Architecture 16 2.3.3 Cyclic Architecture 18 2.3.4 Successive-Approximation (SAR) Architecture 19 2.4 HYBRID ARCHITECTURE 20 2.4.1 Two-Step Architecture 20 2.4.2 Subrange Architecture 21 2.5 SUMMARY OF ADC ARCHITECTURES 22 Chapter 3 The Principle of Subrange ADC (Flash ADC + SAR ADC) 24 3.1 INTRODUCTION FLASH ADC + SAR ADC 24 3.2 ADC ARCHITECTURE AND BUILDING BLOCKS 27 3.2.1 Improvement in Speed and Accuracy 27 3.2.2 Coarse ADC Design 29 3.2.3 Fine SAR ADC 31 3.3 SUMMARY 33 Chapter 4 The Proposed Subrange ADC 35 4.1 Introduction 35 4.2 THE PROPOSED ADC ARCHITECTURE 38 4.2.1 Splitting Monotonic Capacitors Switching Procedure 38 4.2.2 Binary-Scaled Error Compensation Methods 40 4.2.3 Prototype Implementation 42 4.3 Circuit Implementation 45 4.3.1 Sample and Hold Circuit 45 4.3.2 Comparators of Coarse and Fine ADCs 47 4.3.3 SAR Control Logic 49 4.3.4 DAC Control Logic 50 4.3.5 Unit Capacitor 51 4.4 LAYOUT AND MEASUREMENT SETUP 52 4.5 SIMULATION RESULTS 54 4.5 COMPARISON AND DISCUSSION 57 Chapter 5 Conclusion and Future Work 59 Bibliography 60

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