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研究生: 李韋杰
Lee, Wei-Chieh
論文名稱: 透過硬體加速標頭解析之入侵防護系統
Accelerate Intrusion Prevention System Through Offloading Header Decoding
指導教授: 楊竹星
Yang, Chu-Sing
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2026
畢業學年度: 114
語文別: 中文
論文頁數: 36
中文關鍵詞: 智慧網卡硬體卸載入侵防護系統
外文關鍵詞: SmartNIC, Hardware Offload, IPS
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  • 隨著網路技術飛速發展,分散式阻斷服務(DDoS)與零時差漏洞等駭客攻擊手法日益多樣化,資訊安全保護變得至關重要。傳統防火牆無法深入檢測封包,因此需要入侵偵測系統(IDS)與入侵防護系統(IPS)來進行更精密的比對。然而,IPS 在攔截惡意封包時,所有流量都必須經過其判斷,這對系統的吞吐量(Throughput)造成了巨大負擔。以軟體實作的 IPS(如 Suricata)在面對 10 Gbps 以上的高速網路環境時,常會因為 CPU 運算資源飽和而導致封包延遲或遺失。研究發現,CPU 在處理標頭驗證(Header Validation)時,頻繁的 if-else 語法容易引發 branch-miss,嚴重影響效能。 為了解決上述問題,本研究針對 Suricata 系統進行改良,將其解析封包標頭(Decode)的功能,卸載至 Netronome Agilio CX 智慧網卡上執行。

    透過這種硬體卸載架構,系統能減少主機 CPU 的負擔,並提早過濾已知的惡意流量,提升 IPS 整體的處理效率與吞吐量。

    As network technologies advance rapidly, cybersecurity challenges such as Distributed Denial of Service (DDoS) and zero-day exploits have become increasingly sophisticated. While traditional firewalls provide basic protection, Intrusion Prevention Systems (IPS), such as Suricata, are essential for deep packet inspection and real-time threat mitigation. However, in high-speed network environments exceeding 10 Gbps, software-based IPS often encounter significant performance bottlenecks. Research indicates that the CPU spends substantial cycles on header validation tasks, where frequent conditional branching (if-else statements) leads to high branch-miss rates, resulting in packet latency and throughput degradation.

    To address these challenges, this study proposes an hardware-accelerated IPS architecture that offloads the packet header decoding process to a Netronome Agilio CX SmartNIC. By leveraging the programmable flow processing cores of the SmartNIC, the system performs Layer 2 to Layer 4 header parsing and validation directly on the hardware. This offloading strategy effectively reduces the computational burden on the host CPU and mitigates branch-miss penalties. Furthermore, a hardware-based Flow Table is implemented on the NIC to facilitate early filtering and the Respond-Reject mechanism, allowing known malicious traffic to be handled without host intervention.

    Experimental results demonstrate that the proposed architecture consistently outperforms the native Suricata system across various protocols, including TCP, UDP, and ICMP. The performance gain is particularly significant in handling complex UDP-encapsulated traffic and high-load TCP streams. By optimizing resource allocation through a pipelined design within the SmartNIC, this research provides a scalable and efficient solution for robust network security in high-bandwidth infrastructures.

    中文摘要 I Abstract II 誌謝 VI 目錄 VII 表目錄 IX 圖目錄 X 第一章 緒論 1 1-1. 研究背景 1 1-2. 研究動機 2 1-3. 研究目的 3 1-4. 論文架構 3 第二章 背景知識與相關研究 4 2-1. Suricata 4 2-1.1 Suricata Architecture 4 2-1.2 Suricata Rule 5 2-2. SmartNIC 6 2-2.1 Netronome Agilio CX 6 2-2.2 Nvidia Mellanox ConnectX 8 2-3. Extended Berkeley Packet Filter (eBPF) 8 2-3.1 eXpress Data Path (XDP) 9 2-4. Related Work 11 2-4.1 FlexTOE 11 2-4.2 PAMO 13 第三章 系統設計 15 3-1. System Architecture 15 3-1.1 Packet Processing Flowchart 16 3-2. FPC Assignment 18 第四章 實驗設計與結果 19 4-1. 實驗環境 19 4-2. 實驗結果 20 4-2.1 不同協定流量下之吞吐量比較 20 第五章 結果及未來展望 22 5-1. 結論 22 5-2. 未來展望 22 參考文獻 23

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