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| 研究生： |
王家慶 Wang, Jia-Ching |
|---|---|
| 論文名稱： |
具分散式相關電壓位移與多重參考電壓嵌入式比較器之類比數位轉換器 Analog-to-Digital Converters with Distributed Correlated Level Shifting and Multiple-Reference-Embedded Comparator |
| 指導教授： |
郭泰豪
Kuo, Tai-Haur |
| 學位類別： |
博士 Doctor |
| 系所名稱： |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年： | 2022 |
| 畢業學年度： | 110 |
| 語文別： | 英文 |
| 論文頁數： | 95 |
| 中文關鍵詞： | 類比數位轉換器 、導管式逐漸趨近式類比數位轉換器 、逐漸趨近法 、分散式相關電壓位移加權平均技術 、環形放大器 、省略窗口 、次區間式類比數位轉換器 、參考電壓嵌入式比較器 、電容數位類比轉換器 、多重參考電壓嵌入式比較器 |
| 外文關鍵詞： | Analog-to-digital converter (ADC), pipelined-SAR ADC, successive-approximation register (SAR), distributed averaging correlated level shifting, ring amplifier, bypass window, subranging ADC, reference-embedded comparator, capacitive digital-to-analog converter, multiple reference-embedded comparator |
| ORCID： | 0000-0002-3393-4534 |
| 相關次數： | 點閱：55 下載：0 |
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本論文提出多項類比數位轉換器(ADC)之技術，可在提升解析度與操作速度之同時實現極低功耗之規格，並實現於高解析ADC與高速ADC。
針對高解析規格之設計，本作以28-nm CMOS製程實現一14位元130-MS/s兩級導管式逐漸趨近式ADC，其中包含內部各級使用低功耗之逐漸趨近式(SAR)架構之sub-ADC以及一殘值放大器。針對殘值放大器，本作提出具一分散式相關電壓位移加權平均技術(DACLS)之環形放大器作為運算放大器(opamp)，此放大器可大幅減少opamp之有限增益誤差，並且不會對頻寬造成衰減。此外，本作亦實現一改良式省略窗口以節省後級sub-ADC整體功耗達30%以上，並且不影響其操作特性。總和上述技術之優點可使ADC功耗大幅改善。有別於大多數高效能低功耗ADC，本作並不需搭配校正技術，因此本作在複雜度及測試成本方面極具優勢。本作ADC最高可操作於130 MS/s，功耗為0.82 mW。其最佳效能達訊號雜訊失真比(SNDR) 72.5 dB、Walden效能指標 (FoMW) 1.8 fJ/conv.-step及Schreier 效能指標 (FoMS) 181.5 dB。相較現有之中速高解析(輸入頻寬≥40 MHz與SNDR>68 dB) ADC，本作有最佳之FoMW及FoMS。
針對高速規格之設計，本作以28-nm CMOS製程實現一8位元2.7-GS/s電容數位類比轉換器(CDAC)輔助之次區間式(Subranging) ADC。本作以CDAC實現低功耗次區間操作機制，並提出降低CDAC增益誤差及比較器反衝誤差之相應技術，以進一步提升ADC速度。為驗證該技術，本作先實現一2.5-GS/s之原型晶片，功率消耗為3.5 mW。其最佳效能之SNDR 達44.8 dB、FoMW僅為9.8 fJ/conv.-step。相較現有6~10位元之高速單通道(取樣頻率≥1.5 GHz) ADC，本作有最佳之FoMW。為了進一步降低功耗，本作另提出一多重參考電壓嵌入式比較器(MREC)，該比較器除了保有典型參考電壓嵌入式比較器(REC)高速操作之特性，亦透過將數個比較器結合為單一MREC，實現比較器輸入對以及電流源共用。相較於REC，MREC可降低功耗約60%。除此之外，透過橋型CDAC設計，此晶片之輸入電容性負載可以大幅下降，提升ADC操作頻寬。最終，該晶片於2.7 GS/s下，功率消耗進一步降低至3.0 mW，並能提升SNDR之最佳效能至45.9 dB、FoMW僅為6.9 fJ/conv.-step。
In this dissertation, several design techniques for analog-to-digital converter (ADC) are proposed so as to achieve an extremely-low power consumption benchmark while the resolution and operation speed are both improved at the same time. These design techniques are implemented and verified in high-resolution ADCs and high-speed ADCs.
For the high-resolution design, a 14-bit 130-MS/s two-stage pipelined-SAR ADC, including low-power successive approximation register (SAR) sub-ADCs in each stage and a residue amplifier, is proposed and fabricated in 28-nm CMOS technology. For the residue amplifier, a distributed averaging correlated level shifting (DACLS) ring amplifier is proposed and used as the operational amplifier (opamp) to greatly reduce the finite opamp gain error without a degradation of bandwidth. In addition, this work employs a customized bypass-window scheme to reduce the backend sub-ADC power consumption by over 30%. Techniques mentioned above greatly reduce the ADC power consumption. This work does not require any calibration techniques and thereby reduces the testing cost and complexity. The proposed ADC can operate up to 130 MS/s with a 0.82-mW power consumption. This ADC achieves a 72.5-dB signal-to-noise and distortion ratio (SNDR), yielding a Walden (FoMW) and a Schreier (FoMS) figure-of-merits of 1.8 fJ/conv.-step and 181.5 dB, respectively. Compared with prior intermediate-speed high-resolution state-of-the-arts with (Bandwidth≥40 MHz and SNDR≥68 dB), this work achieves the best FoMW and FoMS.
For the high-speed design, an 8-bit 2.7-GS/s capacitive digital-to-analog converter (CDAC)-assisted subranging ADC is proposed and fabricated in 28-nm CMOS technology. A low-power subranging operation is implemented by a CDAC in this work with the proposed countermeasures to reduce the CDAC gain error and the kickback error from comparators for a further speed improvement. To verify these techniques, a prototype 2.5-GS/s ADC is implemented with 3.5 mW and achieves a 44.8-dB SNDR yielding a FoMW of 9.8 fJ/conv.-step. Compared with prior 6~10-bit high-speed single-channel state-of-the-arts with (Sampling rate (FS)≥1.5 GS/s), this work achieves the best FoMW. To further reduce the power consumption, this work proposes a multiple reference-embedded comparator (MREC) which not only retains the high-speed characteristics of a typical REC but also merges several comparators as one MREC with an input pair as well as a tail current source and thereby achieves a ~60% power reduction compared to the REC. In addition, by using a bridged CDAC design, the input capacitive loading is greatly reduced and thus improve the ADC bandwidth. Under a 2.7-GS/s FS, the power consumption of this ADC is compressed to 3.0 mW with an improved SNDR equal to 45.9 dB and a FoMW of 6.9 fJ/conv.-step.
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校內：2027-09-16公開校外：2027-09-16公開