| 研究生: |
丁振國 Ding, Zhen-Guo |
|---|---|
| 論文名稱: |
開迴路導管式類比數位轉換器的研究 A Research on Open-Loop Pipelined Analog-to-Digital Converters |
| 指導教授: |
張順志
Chang, Soon-Jyh |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2006 |
| 畢業學年度: | 94 |
| 語文別: | 英文 |
| 論文頁數: | 89 |
| 中文關鍵詞: | 數位校正 、導管式 、開迴路式 、類比-數位轉換器 |
| 外文關鍵詞: | analog-to-digital converter, pipeline, open-loop, digital calibration |
| 相關次數: | 點閱:87 下載:7 |
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在高速及高解析度的導管式類比數位轉換器中,常常需要採用一個具有高頻寬且高增益的運算放大器以迴授的形式來達到預期的速度及精確度。然而,因為製程的演進而造成操作電壓不斷的下降,設計這樣高規格的運算放大器將面臨很大的挑戰。另一種實現的方式則是以開迴路的運算放大器來實現導管式類比數位轉換器中類比訊號放大的功能。由於開迴路運算放大器架構較為簡單,因此除了在操作速度上可以得到很好的效能之外,同時也相當適合在低電壓下操作。不過,若採用開迴路的方式將會面臨到非線性放大的問題,使得整個導管式類比數位轉換器的精確度難以提昇。
因此在本篇論文中,我們針對非線性放大的問題,提出兩種解決的方式。一種是以根為基礎逼近式數位校正技術,利用簡化非線性的問題以及使用以根為基礎的數位校正技術以達到降低數位演算法的複雜度。除此之外,我們亦提出以線性逼近的方式以降低記憶體的需求。另外一種則是以類比的技巧提升開迴路式放大器的線性度,如此後級數位校正僅需要解決放大器增益偏差的部份,因此可大量簡化數位校正演算法的設計複雜度,使得開迴路導管式類比數位轉換器朝向更低功率的設計。論文中,我們以MATLAB建立行為模式來進行電路效能的預測以及驗證所提出之方法的可行性。
In high speed and high resolution pipelined ADCs, a wide bandwidth and high voltage gain operational amplifier in feedback configuration is necessary to achieve the desired speed and accuracy. However, with the advance of deep submicron technology, the supply voltage scales down continuously. The design of such high performance operational amplifier will face big challenges. An alternative approach is to implement the gain stage in pipelined ADC by using open-loop amplifier. Because of its simple architecture, it is easy to achieve the requirement of high speed operation and suitably operates at the low supply voltage. Nevertheless, the non-linear gain problem of an open-loop amplifier will significantly limit the accuracy of the pipelined ADC. Hence, solving the non-linear gain problem is a big issue by using this open-loop amplifier approach.
Therefore, in this thesis, two methods are proposed to solve the non-linearity problem. The first method is the radix-based approximated calibration method. Through simplifying the non-linear problem and using the radix-based calibration technique, the proposed method can reduce the implementation complexity of calibration algorithm. Besides, we also propose a linear approximation scheme to reduce the required memory size in the digital calibration method. The other one is to enhance the linearity of open-loop amplifier by using some analog linearization techniques. By employing this approach, the back-end calibration part only needs to deal with the gain error of the open-loop amplifier. Therefore, it can simplify the design complexity, and hence save the power consumption, of the back-end digital calibration method. In the thesis, we construct the behavioral models to predict the circuit performance and to demonstrate their efficiency of the proposed methods by using MATLAB simulator.
[1] J. Li, “Accuracy enhancement techniques in low-voltage high-speed
pipelined ADC design,” Ph.D. dissertation, Oregon State University,
Corvallis, Jun. 2004.
[2] A. Karanicolas and H. Lee, “A 15-b 1-Msample/s digitally self-calibrated
pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, pp. 1207-1215, Dec.
1993.
[3] H. Lee, “A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic
ADC,” IEEE J. Solid-State Circuits, vol. 29, pp. 509-515, Apr. 1994.
[4] X. Wang, P. Hurst, and S. Lewis, “A 12-bit 20-Msample/s pipelined analog-
to-digital converter with nested digital background calibration” IEEE J.
Solid-State Circuits, vol. 39, pp. 1799-1808, Nov. 2004.
[5] E. Siragusa and I. Galton, “A digitally enhanced 1.8-V 15-bit 40-
Msample/s CMOS pipelined ADC,” IEEE J. Solid-State Circuits, vol. 39, pp.
2126-2138, Dec. 2004.
[6] J. Li and U. Moon, “A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using
time-shifted CDS technique,” IEEE J. Solid-State Circuits, vol. 39, pp.
1468-1476, Mar. 2004.
[7] J. F. Lin and S. J. Chang, “A 1.8-V 10-bit 100Ms/s pipelined ADC using
modified time-shift CDS technique,” VLSI Design/CAD symposium, 2005.
[8] B. Murmann and B. Boser, “A 12-bit 75-Ms/s pipelined ADC using open-loop
residue amplification,” IEEE J. Solid-State Circuits, vol. 38, pp. 2040-
2050, Dec. 2003.
[9] D. L. Shen and T. C. Lee “A linearity-approximation technique for
digitally-calibrated pipelined A/D converters,” in Proc. IEEE Int. Symp.
Circuits and Syst., Jun. 2005, pp. 1382-1385.
[10] S. Lewis, “Video-rate analog-to-digital conversion using pipelined
architectures,” Ph.D. dissertation, University of California, Berkeley,
1987.
[11] S. Lewis, “Optimizing the stage resolution in pipelined, multistage,
analog-to-digital converters for video applications,” IEEE Trans.
Circuits Syst. II, vol. 39, pp. 516-523, Aug. 1992.
[12] S. Lewis et al., “A 10-b 20-Msample/s analog-to-digital converter,”
IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992.
[13] J. Li and U. Moon, “An extended radix-based digital calibration
technique for multi-stage ADC,” in Proc. IEEE Int. Symp. Circuits and
Syst., May 2003, pp. 829-832.
[14] W. Yang et al., “A 3-V 340-mW 14-b 75-Msample/s CMOS ADC with 85-dB SFDR
at Nyquist input,” IEEE J. Solid-State Circuits, vol. 36, pp. 1931-1936,
Dec. 2001.
[15] T. Cho and P. Gray, “A 10 b, 20Msample/s, 35mW pipelined A/D
converter,” IEEE J. Solid-State Circuits, vol. 30, pp. 166-172, Mar.
1995.
[16] J. F. Lin, “A high speed pipelined A/D converter using modified time-
shifted CDS technique,” master thesis, National Cheng Kung University,
Taiwan, Jul. 2005.
[17] A. Abo, “Design for reliability of low voltage, switched-capacitor
circuits,” Ph.D. dissertation, University of California, Berkeley, 1992.
[18] D. Johns and K. Martin, Analog Integrated Circuit Design, New York:
Wiley, 1997.
[19] T. Cho, “Low-power low-voltage analog-to-digital conversion techniques
using pipelined architectures,” Ph.D. dissertation, University of
California, Berkeley, 1995.
[20] B. Murmann and B. Boser, Digitally Assisted Pipeline ADCs: Theory and
Implementation, Boston, MA: Kluwer Academic, 2004.
[21] B. Razavi, Design of Analog CMOS Integrated Circuit, New York, MA: McGraw-
Hill, 2001.
[22] P. Wambacq and W. Sansen, Distortion Analysis of Analog Integrated
Circuits, Boston, MA: Kluwer Academic, 1998.
[23] P. Gray, P. Hurst, S. Lewis, and R. Meyer, Analysis and Design of Analog
Integrated Circuits, 4th ed. New York: Wiley, 2001
[24] G. Birkhoff and S. Lane, A Survey of Modern Algebra, 5th ed. New York:
Macmillan, 1996.
[25] B. Widrow and S. Stearns, Adaptive Signal Processing, Englewood Cliffs,
NJ: Prentice-Hall, 1985.
[26] B. Murmann, “Digitally assisted analog circuits,” IEEE micro, vol. 26,
pp. 38-47, Mar.–Apr. 2006.
[27] J. Li and U. Moon, “Background calibration techniques for multistage
pipelined ADC’s with digital redundancy,” IEEE Trans. Circuits Syst.
II, vol. 50, pp. 531-538, Sept. 2003.
[28] S. Dupuie and M. Ismail, Analogue IC Design: The Current-Mode Approach,
London, UK: Peter Peregrinus, 1990.
[29] D. Chang, “Design techniques for a pipelined ADC without using a front-
end sample-and-hold amplifier,” IEEE Trans. Circuits Syst. I, vol. 51,
pp. 2123-2132, Nov. 2004.
[30] E. Soenen and E. Geiger, “An architecture and an algorithm for fully
digital correction of monolithic pipelined ADCs,” IEEE Trans. Circuits
Syst. II, vol. 42, pp. 143-153, Mar. 1995.
[31] I. Opris, L. Lewicki, and B. Wong, “A single-end 12-bit 20Msample/s self-
calibrating pipeline A/D converter,” IEEE J. Solid-State Circuits, vol.
33, pp. 1898-1903, Dec. 1998.