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研究生： 吳少棠
Wu, Shao-Tang
論文名稱： 以原子層沉積研製常關式氧化鋁金氧半高電子遷移率電晶體之研究
An Investigation of Normally Off Al2O3 MOS-HEMT by Using Atomic Layer Deposition
指導教授： 王永和
Wang, Yeong-Her
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年： 2017
畢業學年度： 105
語文別： 英文
論文頁數： 91
中文關鍵詞： 高電子遷移率電晶體 、閘極掘入 、原子層沉積 、三氧化二鋁
外文關鍵詞： HEMT, enhancement mode, gate recess, ALD, Al2O3
相關次數： 點閱：143  下載：0 
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    • 此研究以閘極掘入式的製程製作我們的增強型高電子遷移率電晶體,由於閘極蝕刻的影響所造成的缺陷，導致漏電流的增高，以及電流特性下降，我們便利用原子層系統沉積三氧化二鋁，藉由此系統的高品質薄膜及它的高能障來達到抑止漏電流產生的效能，以及元件上的減少缺陷密度。
    藉由成長三氧化二鋁達到高開關電流比，低漏電流的增強式高電子遷移率電晶體。
    因此我們以原子層沉積系統成長三氧化二鋁以及閘極掘入技術完成增強型高電子遷移率電晶體。元件臨界電壓成功提升至0.83 V，最大電流密度達到502 mA/mm，最大轉換電導值達到142 mS/mm，次臨界擺幅與電流開關比為106 mV/dec與5.67×108，閘極漏電流有效降低至 1.08 × 10-6 mA/mm。

    In this research , we have completely frabicated the enhancement mode MOS HEMT by using gate recess process.Since the gate recess process cause the surface defect and surface trap state,induce the gate leakage and lowing the current characteristic . Thus , we use the ALD system to deposite Al2O3 to be our gate dielectic. Using the ALD high quality film and high band gap of Al2O3 to supprese the surface trap density on device and lowing leakage. To frabricate the high on/off ratio , low leakage enhancement mode MOS HEMT .
    By adding Al2O3 as gate dielectric, the maximum drain current density of the E-mode MOSHEMTs achieves as high as 502 mA/mm at VG = 5V.maximum conductance is 142 mS/mm ,subthreshold swing is 106 mV/decade ,on/off ratio can increase to 5.67×108 ,and gate leakage is lowing to 1.08 × 10-6 mA/mm

    中文摘要 ---I Abstract------ II 誌謝----IV List of figures-------- X List of tables--------- XI Chapter 1 Introduction--1 1.1 Background--1 1.2 Motivation--5 1.3 Organization--7 Chapter 2 Heterostructure of AlGaN/GaN--8 2.1 Lattice structure-- 8 2.2 AlGaN/GaN Heterostructure-- 10 2.2.1 Spontaneous polarization effect-- 10 2.2.2 Piezoelectric polarization---13 2.2.3 Two-dimensional electron gas (2DEG)--18 Chapter 3 Experiments and Device Fabrication---26 3.1 Gate-recess process---26 3.1.1 Wet etching---26 3.1.2 Dry etching---28 3.1.3 Etching parameter---31 3.2 ALD deposition of Al2O3---34 3.2.1 Properties of Al2O3---34 3.2.2 ALD system and experiment---36 3.2.3ALD of Al2O3 on Si-Substrate---36 3.3 Experimental equipment---39 1.3.1 Spin coater---39 1.3.2 Mask aligner---40 1.3.3 ICP plasma etching---41 1.3.4 E-gun evaporator---42 1.3.5 RTA system---43 1.3.6 ALD system---44 1.3.7 Semiconductor parameter analyzer---44 3.4.Device fabrication---45 1.3.8 Mesa isolation---46 1.3.9 Source/drain formation---47 1.3.10 Gate-recess etching---48 1.3.11 Al2O3 gate dielectric deposition---49 1.3.12 Gate formation---50 1.3.13 SiNx passivation layer deposition---50 Chapter 4 Results and Discussion---55 4.1 Properties of ALD Al2O3 amd CVD SiNx---55 4.1.1 TEM image---55 4.2 MOSHEMTs with and without passivation performance ---60 4.2.1 Saturation drain current---60 4.2.2 Transfer characteristics and transconductance ----63 4.2.3 Subthreshold swing and on-off ratio---66 4.2.4 Gate leakage current---68 4.3 MOS HEMT of proreties with passivation layer ---70 4.3.1 Gate leakage current---70 4.3.2 Pulse I-V characteristics---73 4.3.3 C-V measurement---80 Chapter 5 Conclusion---82 References---85

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