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研究生: 陳奕呈
Chen, Yi-Cheng
論文名稱: 輔以系統晶片之設計建構適用於PCI匯流排之狀態估測系統
A System-On-a-Chip Design Enhanced with PCI-Bus for State Estimation System
指導教授: 黃世杰
Huang, Shyh-Jier
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2005
畢業學年度: 93
語文別: 中文
論文頁數: 87
中文關鍵詞: 場規劃邏輯陣列PCI匯流排Nios II狀態估測
外文關鍵詞: Nios II, PCI, State Estimation, FPGA
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  •   近年來,由於各項產業蓬勃發展,導致用電需求激增,因此如何維持穩定之供電品質已愈趨重要。本文即著眼於供電系統中,電力網路日益複雜,為求有效監控與管理匯流排系統,勢需快速且精確掌握系統中各節點之狀態,因此提出一可行之解決方案,亦即狀態估測系統之建立。本研究中係以硬體實現狀態估測演算法為系統核心,並採用積體電路之設計,經由場規劃邏輯陣列實現可快速完成估測運算之估測模組,同時並導入系統晶片之設計概念,完成PCI橋接電路與Nios II處理器之整合,以建立適用於PCI匯流排之狀態估測系統。本系統經模擬測試及分析,證實其已可快速推算各節點之狀態值,對於系統監測人員於電力系統運轉狀態之掌握,確有極高之助益,應可協助提昇電力系統運轉可靠度,裨於提供穩定之供電品質。

     With the fast development of modern industry, electricity demand is seen highly increased nowadays. The provision of electric power of high quality is thus deemed more important, hence motivating the study of this thesis that is aimed at solving the state estimation with a more efficient strategy. Based on such a goal, the hardware realization of state estimation is proposed where the field programmable gate array (FPGA) integrated with the concept of system-on-a-chip is employed. Meanwhile, the PCI bridge circuit as well as the Nios II processor is also combined in the proposed structure with the anticipation of reaching a state estimation system suitable for the PCI bus. The proposed system has been tested through the simulation validation. Test results have confirmed that the proposed approach is capable of grasping the states of a power system, which would be also beneficial for the increment of power system reliability, ensuring a supplying power of high quality.

    中文摘要                   I 英文摘要                   II 誌謝                    III 目錄                     IV 表目錄                    VI 圖目錄                   VII 第一章 緒論                 1   1.1 研究背景與動機            1   1.2 研究方法               3   1.3 論文架構               4 第二章 相關技術               5   2.1 狀態估測演算法            5   2.2 Nios II簡介             9     2.2.1 集成開發環境         16 第三章 系統架構               19   3.1 狀態估測系統            19   3.2 狀態估測之運算架構         21     3.2.1 弦波函數模組         23     3.2.2 非線性量測函數模組      25     3.2.3 Jacobian矩陣運算模組     27     3.2.4 弦波函數仲裁器        29     3.2.5 K矩陣與目標函數運算模組    31     3.2.6 LU分解模組          32     3.2.7 線性求解模組         36     3.2.8 狀態估測控制器        38   3.3 介面架構設計            39     3.3.1 Nios II之記憶體映射      40     3.3.2 Nios II之軟體架構       42   3.4 PCI驅動程式架構           44 第四章 實驗結果               46   4.1 估測模組之驗證           46     4.1.1 平行處理           47     4.1.2 管線程序  49     4.1.3 線性求解           51     4.1.3 估測模組之驗證結果      53   4.2 發展平台              56     4.2.1 Nios II之建立         60     4.2.2 PCI橋接電路          61   4.3 合成結果              64   4.4 驗證環境              67   4.5 實作結果              68 第五章 結論與未來研究方向          75   5.1 結論                75   5.2 未來研究方向            75 參考文獻                   77 附錄A                    80 作者簡介                   87

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