| 研究生: |
陳奕呈 Chen, Yi-Cheng |
|---|---|
| 論文名稱: |
輔以系統晶片之設計建構適用於PCI匯流排之狀態估測系統 A System-On-a-Chip Design Enhanced with PCI-Bus for State Estimation System |
| 指導教授: |
黃世杰
Huang, Shyh-Jier |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電機工程學系 Department of Electrical Engineering |
| 論文出版年: | 2005 |
| 畢業學年度: | 93 |
| 語文別: | 中文 |
| 論文頁數: | 87 |
| 中文關鍵詞: | 場規劃邏輯陣列 、PCI匯流排 、Nios II 、狀態估測 |
| 外文關鍵詞: | Nios II, PCI, State Estimation, FPGA |
| 相關次數: | 點閱:98 下載:0 |
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近年來,由於各項產業蓬勃發展,導致用電需求激增,因此如何維持穩定之供電品質已愈趨重要。本文即著眼於供電系統中,電力網路日益複雜,為求有效監控與管理匯流排系統,勢需快速且精確掌握系統中各節點之狀態,因此提出一可行之解決方案,亦即狀態估測系統之建立。本研究中係以硬體實現狀態估測演算法為系統核心,並採用積體電路之設計,經由場規劃邏輯陣列實現可快速完成估測運算之估測模組,同時並導入系統晶片之設計概念,完成PCI橋接電路與Nios II處理器之整合,以建立適用於PCI匯流排之狀態估測系統。本系統經模擬測試及分析,證實其已可快速推算各節點之狀態值,對於系統監測人員於電力系統運轉狀態之掌握,確有極高之助益,應可協助提昇電力系統運轉可靠度,裨於提供穩定之供電品質。
With the fast development of modern industry, electricity demand is seen highly increased nowadays. The provision of electric power of high quality is thus deemed more important, hence motivating the study of this thesis that is aimed at solving the state estimation with a more efficient strategy. Based on such a goal, the hardware realization of state estimation is proposed where the field programmable gate array (FPGA) integrated with the concept of system-on-a-chip is employed. Meanwhile, the PCI bridge circuit as well as the Nios II processor is also combined in the proposed structure with the anticipation of reaching a state estimation system suitable for the PCI bus. The proposed system has been tested through the simulation validation. Test results have confirmed that the proposed approach is capable of grasping the states of a power system, which would be also beneficial for the increment of power system reliability, ensuring a supplying power of high quality.
[1] A. J. Wood and B. F. Wollenberg, Power Generation, Operation, and Control, Second Edition, John Wiley & Sons, Inc., New York, USA, 1996.
[2] A. R. Bergen, Power System Analysis, Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1986.
[3] A. Monticelli, “Electric Power System State Estimation”, Proceedings of the IEEE, Vol. 88, No. 2, February 2000, pp. 262-282.
[4] H. M. Merrill and F. C. Schweppe, “Bad Data Suppression in Power System Static State Estimation”, IEEE Transactions on Power Apparatus and Systems”, Vol. 90, No. 6, November-December 1971, pp. 2718-2725.
[5] A. Monticelli, State Estimation in Electric Power Systems: A Generalized Approach, Kluwer Academic Publishers, Boston, USA, 1999.
[6] R. E. Larson, W. F. Tinney, and J. Peschon, “State Estimation in Power Systems, Part I: Theory and Feasibility”, IEEE Transactions on Power Apparatus and Systems, Vol. 89, No. 3, March 1970, pp. 345-352.
[7] M. G. Arnold, Verilog Digital Computer Design - Algorithm into Hardware, Prentice Hall PTR, New Jersey, USA, 1999.
[8] K. Coffman, Real World FPGA Design with Verilog, Prentice Hall, New Jersey, USA, 2000.
[9] S. P. Beaumont”,The SoC Challenge”, Electronics & Communication Engineering Journal, Vol. 13, No. 6, pp. 234-235, December 2001.
[10] C. Rowen, “Reducing SoC Simulation and Development Time”, Computer, Vol. 35, No. 12, pp. 29-34, December 2002.
[11] R. C. Pires, A. Simoes Costa, and L. Mili, “Iteratively Reweighted Least-Squares State Estimation through Givens Rotations”, IEEE Transactions on Power Systems, Vol. 14, No. 4, November 1999, pp. 1499-1507.
[12] E. Handschin, F. C. Schweppe, J. Kohlas, and A. Fiechter, “Bad Data Analysis for Power System State Estimation”, IEEE Transactions on Power Apparatus and Systems, Vol. 94, No. 2, March-April 1975, pp. 329-337.
[13] F. C. Schweppe and J. Wildes”,Power System Static State Estimation, Part I: Exact Model”, IEEE Transaction on Power Apparatus and Systems, Vol. 89, January 1970, pp. 120-125.
[14] Altera Company, http://www.altera.com/products/ip/processors/nios2/
overview/ni2-overview.html
[15] Altera Company, “Nios II Processor Reference Handbook”, Version 5.0, May 2005.
[16] Altera Company, “Avalon Bus Specification Reference Manual”, Version 2.1, January 2003.
[17] Altera Company, “Nios II Software Developer's Handbook”, Version 5.0, May 2005.
[18] Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Prentice Hall, Upper Saddle River, New Jersey, USA, 2003.
[19] B. Zeidman, Verilog Designer's Library, Prentice Hall, Upper Saddle River, New Jersey, USA, 1999.
[20] S. Palnitkar, Verilog HDL, Second edition, Prentice Hall, Upper Saddle River, New Jersey, USA, 2003.
[21] C. Nikias, A. Chrysafis and A. Venetsanopoulos, “The LU Decomposition Theorem and Its Implications to the Realization of Tow-Dimensional Digital Filters”, IEEE Transactions on Acoustics, Speech, and Signal Processing, Vol. 33-3, June 1985, pp. 694-711.
[22] E. Casseau and D. Degrugillier, “A Linear Systolic Array for LU Decomposition”, International Conference on VLSI Design, VLSI Design' 94, Calcutta, India, January 1994, pp. 353-358.
[23] K. Hwang and Y. H. Cheng, “Partitioned Matrix Algorithm for VLSI Architecture Systems”, IEEE Transactions on Computers, Vol. 31, No. 4, December 1982, pp. 1215-1224.
[24] Jungo Company, “WinDriver v6.00 User’s Guide”, March 2003.
[25] Mentor Graphics Company, “ModelSim User’s Manual”, Version 5.7d, May 2003.
[26] Altera Company, “PCI Development Kit, Stratix Edition Getting Started User Guide”, Version 1.0.0, May 2003.
[27] Altera Company, “Stratix PCI Development Board Data Sheet”, Version 1.0, May 2003.
[28] Altera Company, “Quartus II Development Software Handbook”, Version 4.0, May 2004.
[29] Altera Company, “Nios II Hardware Development Tutorial”, Version 1.2, Jan 2005.
[30] Altera Company, “Altera Embedded Peripherals Handbook”, Version 5.0, May 2005.
[31] Intel Company, “PCI Local Bus Specification”, Revision 2.2, December 1998.
[32] OpenCores Organization, “PCI IP Core Specification”, Revision 1.2, January 2004.
校內:2055-06-23公開