本研究中我們成功利用液相沉積和濺鍍技術，堆疊高品質超薄三氧化二鋁和二氧化鈦研製閘極介電層堆疊金氧半氮化鋁鎵/氮化鎵高電子遷移率電晶體，藉由三氧化二鋁高能隙和高崩潰電場的特性，有效抑制閘極漏電流的產生並提高崩潰電壓。此外，堆疊高介電常數二氧化鈦，能進一步的抑制閘極漏電流和提高崩潰電壓，同時維持低等效氧化層厚度。藉由比較傳統型氮化鋁鎵/氮化鎵高電子遷移率電晶體及相同物理厚度之二氧化鈦介電層氮化鋁鎵/氮化鎵高電子遷移率電晶體，成功使閘極介電層堆疊金氧半氮化鋁鎵/氮化鎵高電子遷移率電晶體降低閘極漏電流一到二個數量級並提升崩潰電壓大約60伏特，而其他電性也有所提升。
此外，為了避免額外功率的損耗及減化電路的偏壓設計，我們利用閘極掘入的方式，減少電晶體閘極下方的二維電子氣濃度，成功使三氧化二鋁/二氧化鈦閘極堆疊金氧半氮化鋁鎵/氮化鎵高電子遷移率電晶體臨界電壓有效提升至0.67 V；最大電流密度可達391 mA/mm，轉導值則為100 mS/mm，電流開關比為4.93×105，閘極漏電流及崩潰電壓則為1.35×10-6A/mm和172 V。

In this study, AlGaN/GaN metal–oxide–semiconductor high electron mobility transistors (MOSHEMTs) with stacked high-quality ultra-thin Al2O3/TiO2 gate dielectrics have been successfully fabricated by liquid-phase deposition/sputtering techniques. The high bandgap and high breakdown field of Al2O3 dielectric can effectively suppress gate leakage current and increase breakdown voltage. However, stacking high-k TiO2 dielectric further suppresses the gate leakage current, enhancing the breakdown voltage and maintaining a low equivalent oxide thickness. The gate leakage current is successfully reduced by 1–2 orders of magnitude, and the breakdown voltage increased by approximately 60V compared with conventional AlGaN/GaN HEMTs and AlGaN/GaN MOSHEMTs with a single TiO2 dielectric layer of the same physical thickness. Other performances are also enhanced.
To avoid additional power consumption and simplify bias design of the circuit, gate recess process is used to reduce of the density of the two-dimensional electron gas (2DEG) under the gate region. Therefore, the threshold voltage of gate dielectric stack Al2O3/TiO2 AlGaN/GaN MOSHEMTs is effectively improved to 0.67 V. The maximum drain current density reaches 391 mA/mm. The maximum transconductance is 100 mS/mm. The on/off ratio is 4.93×105. The gate leakage current and breakdown voltage are 1.35×10−6 A/mm and 172 V, respectively.

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