隨著5G時代來臨，數位電路的頻率逐漸增加，例如CPU時脈的主要頻率多為2.4GHz或以上，訊號切換在PCB內部金屬層之間形成的同步切換雜訊不容忽視。以週期性的內嵌式電磁能隙結構抑制雜訊，探討過往文獻中，假設干擾為平面波所推導出的電磁能隙結構模型、公式，進行公式計算與HFSS模擬驗證。在公式計算中，以MATLAB計算文獻中電磁能隙結構的傳輸線模型，以此得到電磁能隙結構的截止帶頻率範圍。模擬驗證時，建立HFSS模擬流程，以HFSS eigenmode模擬無窮週期時，電磁能隙結構的頻散圖(dispersion diagram)，以此得到截止帶頻率，再以HFSS driven modal 模擬有限週期，wave port 1饋入的平面波經過M×N個unit cell組成的電磁能隙結構之後傳遞到wave port 2上，藉由S_21參數得知截止帶頻率，最後，同樣模擬有限週期，以incident cylindrical wave作為雜訊源，離雜訊源一段距離為觀測點，觀測點的電場振幅E_O除以雜訊源的電場振幅E_N取dB值，即20log⁡(E_O/E_N )為衡量截止帶頻率的標準，藉由柱面波模擬結果與假設平面波的公式計算、模擬結果做比較，評估平面波假設的正當性與有效性。由柱面波模擬，得知雜訊的大小會隨著與雜訊源的距離而變化，電磁能隙結構的擺放數目也並非越多越好，必須藉由模擬得知，在離雜訊源某一距離之下，最佳的unit cell數目，這是過往文獻中假設干擾波為平面波時，未能得到的結論。

To suppress the simultaneous switching noise, periodic electromagnetic bandgap (EBG) structures have been studied in previous literature. The electromagnetic bandgap structure formula is derived from the assumptions of one-direction planar waves and infinite periodicity. One can use HFSS eigenmode to consider two-direction propagation to obtain the dispersion diagram for infinite periodicity. In this study, we use HFSS to simulate a metal parallel plate with 80mm length, 108mm width, and 1mm height. The dielectric is FR4 embedded electromagnetic bandgap structures composed of M×N unit cells. For planar wave simulation, the stopband frequency is obtained from the S_21 parameter. When embedded 12×2 unit cells, the 20dB stopband frequency is similar to the result of infinite periodicity. The farther the distance of propagation, the more significant the wave attenuation. For cylindrical wave simulation, an incident cylindrical wave is used as the noise source, and two observation points are selected. One is close to the source, and the other is far from the source. When the distance from the source becomes farther, the attenuation intensity of the electric field is not necessarily greater. The optimal number of unit cells is determined by noise frequency and the distance from noise. The result is different from that of planar assumption due to it’s not appropriate in reality. The optimal number of unit cells should be designed through software simulation.

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