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研究生： 江凱祥
Chiang, Kai-Hsiang
論文名稱： 一個基於電荷分享切換方式之低功耗逐漸趨近式類比數位轉換器
An Energy-Efficient SAR ADC with Charge Sharing Switching Method
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2013
畢業學年度： 102
語文別： 英文
論文頁數： 88
中文關鍵詞： 類比數位轉換器 、逐漸趨近式類比數位轉換器 、電荷分享切換方式 、以時間為基準的視窗電路 、高能源轉換效率
外文關鍵詞： analog-to-digital converter, successive-approximation-register ADC (SAR ADC), charge sharing switching method, time-based window, high energy efficiency
相關次數： 點閱：92  下載：15 
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    • 近年來，可攜式、可穿戴式以及行動式電子設備的發展日益蓬勃，它們的應用都有著低耗能的共同訴求，使得低功耗積體電路設計相關的研究備受重視。類比數位轉換器是單晶片系統 重要區塊之一，在中解析、低速度需求的應用面上(如:生醫電子)，逐漸趨近式類比數位轉換器因其架構上的特點，使得它非常適合低電壓操作並達到高轉換效率。
    本篇論文提出的逐漸趨近式類比數位轉換器主要包含兩種技巧來改善低操作電壓的情況，並提高整體電路的轉換效率。 基於電荷重新分佈原理(Charge Sharing Switching (CSS) method)的切換方式利用原有電容陣列中儲存的電荷進行切換以降低其功耗；提出的切換方式，也改善了傳統電荷分享式電容陣列中線性度不足的問題。
    由於逐漸趨近式類比數位轉換器是重複使用一個比較器來進行解碼，整體電路中數位電路所佔比例非常高，可以透過降低操作電壓來減少功率消耗。不過，操作電壓的降低也意味著訊號雜訊比(SNR)會更加惡化，使得比較器設計需有著更高的解析度。倘若一個十位元的逐漸趨近式類比數位轉換器，整個轉換過程都使用高解析的比較器是十分耗能。基於此，本論文提出可調解析度比較器架構，結合固定視窗概念，優化比較器的功耗表現並擁有足夠的雜訊抑制能力。此外，視窗電路免去了不必要的電容切換以節省能量，並改善了線性度。
    一個包含十位元、每秒取樣10萬次逐漸趨近式類比數位轉換器的測試晶片以台積電90奈米製程所完成，其電路核心面積約為0.02mm2。實測效能顯示，在0.4伏特操作電壓以及奈奎斯特輸入頻率下，有效位元為8.89位元，功耗只有107奈瓦，推算得到的轉換效率為2.23 fJ/conversion-step。

    Recently, energy-limited applications such as wireless sensing devices of portable or wearable, mobile products, etc., require high-efficient ADCs to extend the battery life of these devices. With the technology downscaling, low-voltage ADCs are required for implementation of low supply SoC design. SAR ADCs are suitable for these applications due to their excellent power efficiency and low-voltage potential compared to other ADCs architectures (e.g., pipelined ADC).
    This work presents a low-voltage and energy-efficient 10-bit SAR ADC with two techniques. The proposed charge sharing switching (CSS) method can reduce the switching power by reusing the energy stored in CDAC without the deteriorated linearity problem in conventional charge sharing SAR ADC. Meanwhile, decreasing the supply voltage is helpful in reducing the power dissipation of SAR ADC. However, low supply voltage may deteriorate the signal-to-noise ratio (SNR) due to small signal power and poor accuracy of the comparator. A flexible comparator with time-based window function is proposed to achieve fast comparison as well as low-noise requirements with small power dissipation. The flexible comparator with time-based window function can alleviate the comparison error without penalty of huge power consumption. Furthermore, the time-based window function can minimize the conversion error induced by insufficient DAC settling time and improve the ADC linearity by skipping unnecessary capacitor switching.
    The proposed 10-bit SAR ADC operates at 100kS/s with 0.4V supply voltage in 90nm CMOS process. The measurement results show that the prototype ADC achieves 8.89 effective number of bit (ENOB) with Nyquist rate input and consumes only 107nW. The figure-of-merit (FOM) is 2.23fJ/conversion-step. The active area (excluding output buffers) of the prototype ADC is 175μm x 110μm.

    Abstract I Table of Contents VI List of Figures IX List of Tables XI Chapter 1 Introduction 1 1.1 BACKGROUND: EFFICIENCY OPTIMIZED ADCS 1 1.2 MOTIVATION 2 1.3 RESEARCH OBJECTIVES AND THESIS ORGANIZATION 3 Chapter 2 Fundamentals of Analog-to-Digital Converter 5 2.1 ANALOG-TO-DIGITAL CONVERSION 5 2.2 SAMPLING THEORY 6 2.3 QUANTIZATION ERROR (NOISE) 8 2.4 RESOLUTION AND ACCURACY 10 2.5 ADC SPECIFICATIONS 11 2.5.1 STATIC SPECIFICATIONS 11 2.5.1.1 Offset 11 2.5.1.2 Gain Error 12 2.5.1.3 Nonlinearities 13 2.5.1.3.1 Differential Non-Linearity (DNL) 13 2.5.1.3.2 Integral Non-Linearity (INL) 14 2.5.2 DYNAMIC SPECIFICATIONS 16 2.5.2.1 SNR and SNDR 16 2.5.2.2 Spurious-Free Dynamic Range (SFDR) 17 2.5.2.3 Effective Number of Bits (ENOB) 18 2.5.2.4 Figure-of-Merit (FOM) 18 Chapter 3 Nyquist Rate Analog-to-Digital Converter 19 3.1 FLASH ADCS 19 3.2 SUBRANGING (TWO-STEP) ADCS 21 3.3 PIPELINE ADCS 22 3.4 Successive Approximation Register ADCs 23 3.5 Summary 25 Chapter 4 Low Power and Low Voltage SAR ADC Topologies 26 4.1 SAR ADC WITH CAPACITIVE DAC 27 4.1.1 Charge Sharing SAR ADC 27 4.1.2 Charge Redistribution SAR ADC 28 4.1.3 State-of-the-Art Performances and Comparison 30 4.2 THE SWITCHING PROCEDURE OF SAR ADC 30 4.2.1 Monotonic Capacitor Switching Procedure 31 4.2.2 Vcm-based Capacitor Switching Procedure 32 4.2.3 Splitting-Monotonic Capacitor Switching Procedure 33 4.2.4 State-of-the-Art Performances of monotonic, Vcm-based and splitting-monotonic switching 35 4.3 SMALL CDAC WITH LINEARITY IMPROVING TECHNOLOGY 35 4.3.1 Segmented Capacitive D/A Converter 35 4.3.2 Window Function in Binary Search Algorithm 36 4.3.3 State-of-the-Art Performances of segmented capacitive DAC and window function in SAR converters 37 4.4 LOW VOLTAGE SAR ADC CONSIDERATIONS 38 4.4.1 NOISE PROBLEM 38 4.4.1.1 PRE-AMPLIFIER BASED COMPARATOR 39 4.4.1.2 FLEXIBLE COMPARATOR 40 4.4.1.3 MAJORITY VOTING FUNCTION 41 4.4.2 SUB-THRESHOLD REGION PROBLEM 42 4.4.2.1 TIME-INTERLEAVED SAMPLING TECHNIQUE 43 4.4.2.2 DOUBLE-BOOTSTRAPPED SWITCH 43 Chapter 5 A 10b 100kS/s SAR ADC with Charge Sharing Switching Method 45 5.1 OVERVIEW OF THE PROPOSED SAR ADC 45 5.2 ARCHITECTURE OF THE PROPOSED SAR ADC 47 5.3 CHARGE SHARING SWITCHING METHOD 49 5.4 HIGH EFFICIENT DYNAMIC COMPARATOR 52 5.5 TIME-BASED WINDOW FUNCTION 56 5.6 CIRCUIT-LEVEL DESIGN 57 5.6.1 DOUBLE BOOTSTRAPPED SAMPLING SWITCH 57 5.6.2 COMPARATOR 59 5.6.3 CAPACITIVE DAC 64 5.6.4 TIME-BASED WINDOW FUNCTION CIRCUIT 67 5.6.5 ASYNCHRONOUS CLOCK GENERATOR 68 5.6.6 SAR LOGIC CONTROLLER 69 5.6.7 DECODER 71 5.7 CHIP FLOOR PLAN AND LAYOUT 71 5.8 POST-LAYOUT SIMULATION RESULTS 73 5.9 SUMMARY 74 Chapter 6 Experimental Results 75 6.1 INTRODUCTION 75 6.1.1 PCB DESIGN CONSIDERATION 75 6.1.2 MEASUREMENT SETUP 77 6.2 MEASUREMENT RESULTS 78 6.2.1 MICROGRAPH OF CHIP 78 6.2.2 MEASUREMENT PERFORMANCE 79 Chapter 7 Conclusions and Future Work 83 7.1 CONCLUSION OF PROPOSED SAR ADC 83 7.2 PERSPECTIVE FUTURE WORK 84 Bibliography 85

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