本論文針對直流-直流降壓轉換器研究快速負載暫態響應，及快速動態電壓調節暫態響應技術。
本論文對快速負載暫態響應針對補償器設計、及暫態脈波寬度調變設計分別提出可重組頻寬、及固定暫態脈波寬度技術使直流-直流降壓轉換器在全負載變動範圍中以簡化快速暫態響應器的設計並達到最大暫態電壓抖動最小化。在補償器設計部份，直流-直流降壓轉換器在輕載操作常以降頻提升效率，本論文提出切換式電容補償器使補償係數隨切換頻率重組，使系統在考量輕載降頻提升效率的同時仍可最大化迴路頻寬以提升暫態響應速度並兼顧穩定度。將所提技術以0.35μm CMOS製程實現於 電流模式控制架構，此晶片面積為0.91mm2，量測結果顯示，在效率部份最高達到96.3%，在暫態響應部份於700mA負載變動下將暫態電壓抖動抑制至75mV且使暫態響應時間達到5μs。
在暫態脈波寬度調變設計部份，分析最佳化暫態電壓抖動對所有負載變動關係，找出可使暫態電壓抖動最小化之固定暫態脈波開/關時間對負載變動關係，簡化快速負載暫態響應控制器設計且使最大暫態電壓抖動最小化。本論文亦對電流模式控制下提出補償器電壓設置控制，加速補償器反應速度，使所提直流-直流降壓轉換器進一步改善暫態響應時間。所提技術以0.35μm CMOS製程實現於電流模式控制架構，此晶片面積為0.91mm2，量測結果顯示在最大1A負載變動下分別於輕載轉重載將暫態電壓抖動自165mV抑制至75mV且響應時間達3.6μs、重載轉輕載之抖動自75mV降低至45mV，響應時間為1.4μs。與其他頂尖文獻之電流模式控制相比達到最快負載暫態響應速度。
本論文對快速動態電壓調節暫態響應提出可重組暫態響應最佳化設計，研究分別對動態電壓調節、及負載暫態響應最佳化之關係，利用兩者相似部份提出可重組暫態響應最佳化設計。模擬結果顯示在1V-1.8V、及1.8V-1V動態電壓調節下之響應時間分別為182ns、及192ns，其暫態響應表現逼近理論最小值。

This dissertation is focused on the research of the methods for achieving fast load- and DVS-transient response.
For fast load-transient response, a reconfigurable bandwidth method, and a constant on/off-time control during transient is proposed in this dissertation for the compensator and the pulse width of the PWM during transient, respectively, to minimize the maximum load-transient undershoot (ΔVUS) and overshoot (ΔVOS) over the entire load-current change (ΔILoad) range while simplifying the fast-transient controller design. For the compensator design, the dc-dc buck converters operated in light load are usually decreased the switching frequencies for improving the light-load efficiency. Hence, the switched-capacitor (SC) compensator is proposed for reconfiguring the compensation coefficients according to the switching frequencies for maximizing the loop bandwidth while maintaining the stability. The proposed methods are integrated with a current-mode control scheme. Fabricated in 0.35μm CMOS process, this chip occupying 0.91mm2 achieves 96.3% peak efficiency. A 5μs settling time (tsettle) is measured with 75mV undershoot for a 700mA ΔILoad.
For the pulse width of the PWM during transient, the relationship between the ΔVUS/ΔVOS and ΔILoad is analyzed in this dissertation to attain a relationship between the constant on/off-time during transient and ΔILoad. Therefore, maximum ΔVUS/ΔVOS over the entire ΔILoad range is achieved while the controller design is simplified. A voltage-setting control (VSC) method is proposed for further shortening tsettle by accelerating the compensator`s response speed. This work is implemented in 0.35μm CMOS process with 0.91mm2 area. The measured maximum ΔVUS, and ΔVOS for ±1A-ΔIMAX are respectively suppressed from 165mV to 75mV with 3.6μs tsettle and 75mV to 45mV with 1.4μs tsettle. Compared to the prior current-mode control scheme, the fastest response speed is achieved.
For fast DVS-transient response, a reconfigurable transient optimizer (RTO), which is developed by the research of the similarities between two control methods for individually optimizing DVS- and load- transient responses, is proposed in this dissertation. Simulation results shows a 1-to-1.8 V (1.8-to-1 V) DVS transient, tsettle is 182 ns (192 ns), and thereby the DVS-transient response in this dissertation approximates to its theoretical minimum.

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