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研究生： 李其曄
Lee, Chi-Yeh
論文名稱： 利用貝式平滑分數與動差估計法之小延遲缺陷診斷
Small-Delay Defect Diagnosis Using Bayes-Smoothed Scoring and Method of Moments Estimation
指導教授： 李昆忠
Lee, Kuen-Jong
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2025
畢業學年度： 113
語文別： 英文
論文頁數： 49
中文關鍵詞： 小延遲缺陷 、時序感知診斷 、假路徑 、診斷向量 、經驗貝氏 、ATE 、ATPG 、VLSI 測試
外文關鍵詞： small delay defect, timing-aware diagnosis, false path, diagnosis pattern, empirical Bayes, ATE, ATPG, VLSI test
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    • 本論文提出針對晶片中小延遲缺陷之第二輪診斷流程。當第一輪診斷流程無法確定缺陷位置，或信心不足時，即可使用第二輪診斷流程。本流程首先以歷史資料求出真實缺陷分數邊界以篩選第一輪候選，再產生成對之假路徑約束測試向量以選擇性激發或遮蔽剩餘候選。藉由比對第二輪量測晶片與模擬結果獲得評估參數，最後以經驗貝氏平滑算法結合動差估計法得到候選分數，再以乘法算法整合一、二輪診斷結果。實驗結果顯示，在六組開源基準電路（5 k–342 k cells）上，多候選之含糊案例的正確診斷率由 74 % 提升至 83 %，且未出現任何由正確轉為錯誤的案例；每次診斷僅需約 9–40 分鐘，外加一次短暫 ATE 重測，對既有診斷流程的額外負擔甚低。

    Small delay defects (SDDs) have emerged as a dominant yield and quality limiter in nanometer ICs, yet traditional transition-fault (TF) diagnosis—rooted in a single-cycle delay model—often leaves several high-scoring but indistinguishable candidates. This work introduces a fast second-pass automated-test-equipment (ATE) diagnosis flow that (1) filters the first-pass candidate list with an adaptive score-margin learned from historical data, (2) generates pair-wise false-path-constrained launch-on-capture patterns that selectively excite or mask each surviving candidate, (3) re-measures the chip under test, and (4) re-scores every candidate with empirical-bayes smoothed scoring and a multiplicative scoring of first- and second-pass evidence.
    Across six open-source benchmarks (5 k–342 k cells), the proposed flow raises the correct cases rate from 74 % to 83 % on the previously ambiguous multi-candidate cases while never degrading any case that was already correct in the first pass (0 correct-to-incorrect flips). Each diagnosis completes in ≈9–40 min of runtime plus a single short ATE retest, adding only modest overhead to conventional silicon debug.

    摘要 i Abstract ii 致謝 iv TABLE OF CONTENTS v TABLES vi TABLE OF FIGURES vii CHAPTER 1 Introduction 1 CHAPTER 2 Background 3 CHAPTER 3 Proposed Diagnosis Flow 5 CHAPTER 4 Margin Filtering 8 CHAPTER 5 Candidate Pairing & False-Path Pattern Generation 11 5.1 False-Path Constraint Behavior and Validation 11 5.2 Fault Model and Pattern Generation Settings 14 CHAPTER 6 Second-Pass ATE 15 CHAPTER 7 Timing-Aware Simulation & Representative Selection 16 7.1 Delay Injection and Simulation Procedure 16 7.2 Selecting a Representative Outcome for Each Candidate 17 CHAPTER 8 Empirical-Bayes Scoring & Multiplicative Scoring 19 8.1 Overview of the Integration Process 19 8.2 Empirical-Bayes Scoring 20 8.3 Multiplicative Scoring 24 CHAPTER 9 Experimental Results 26 CHAPTER 10 Conclusions 37 References 38

    [1] S. Holst et al., “Variation-Aware Small Delay Fault Diagnosis on Compressed Test Responses,” Proc. ITC, 2019.
    [2] J.-H. Jian (2025), “Accurate Timing-Aware Small Delay Defect Diagnosis with Multi-Level Candidate Reduction and Variation Consideration,” (Master’s thesis, National Cheng Kung University).
    [3] K-J. Lee, C-H. Wu, and T-Y. Hou, “An Efficient Procedure to Generate Highly Compact Diagnosis Patterns for Transition Faults,” IEEE TCAD, vol. 41, no. 3, Mar. 2022.
    [4] S. K. Goel, N. Devta-Prasanna, and R. P. Turakhia, “Effective and Efficient Test Pattern Generation for Small Delay Defect,” VTS, 2009.
    [5] X. Yu and R. D. Blanton, “Diagnosis-Assisted Adaptive Test,” IEEE TCAD, vol. 31, no. 9, Sept. 2012

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